From ffd768ce865e330a631c56d63c6f472e9ad85511 Mon Sep 17 00:00:00 2001
From: Ahmed Irfan <ahmedirfan1983@gmail.com>
Date: Fri, 3 Jan 2014 10:52:44 +0100
Subject: btor

---
 btor.ys | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 btor.ys

(limited to 'btor.ys')

diff --git a/btor.ys b/btor.ys
new file mode 100644
index 000000000..11833e2ac
--- /dev/null
+++ b/btor.ys
@@ -0,0 +1,20 @@
+#design should be loaded before executing 
+
+#high level synthesis
+#################
+#converting processes to cells
+proc; 
+opt;
+#converting pmux to mux
+techmap -map techlibs/common/pmux2mux.v;
+opt;
+#converting asyn memory write to syn memory
+memory_dff; 
+opt;
+#flatten design
+flatten;
+opt;
+#adding temporary wires for cell ports
+scatter;
+#writing btor
+write_btor design.btor;
-- 
cgit v1.2.3


From 661b5a993ebbe331c8d4085372622587e1712ab4 Mon Sep 17 00:00:00 2001
From: Ahmed Irfan <ahmedirfan1983@gmail.com>
Date: Tue, 14 Jan 2014 12:03:53 +0100
Subject: BTOR backend

---
 btor.ys | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

(limited to 'btor.ys')

diff --git a/btor.ys b/btor.ys
index 11833e2ac..5293ed63b 100644
--- a/btor.ys
+++ b/btor.ys
@@ -4,7 +4,8 @@
 #################
 #converting processes to cells
 proc; 
-opt;
+opt; opt_const -mux_undef; opt;
+rename -hide;;;
 #converting pmux to mux
 techmap -map techlibs/common/pmux2mux.v;
 opt;
@@ -12,9 +13,9 @@ opt;
 memory_dff; 
 opt;
 #flatten design
-flatten;
-opt;
-#adding temporary wires for cell ports
-scatter;
+flatten;;;
+#cell output to be a single wire
+splitnets -driver;
+opt;;;
 #writing btor
 write_btor design.btor;
-- 
cgit v1.2.3


From 9a689f33a56d4b351bab021989f79e9b19500c62 Mon Sep 17 00:00:00 2001
From: Ahmed Irfan <irfan@ubuntu.(none)>
Date: Fri, 17 Jan 2014 19:32:35 +0100
Subject: verilog default options pull shift operator width issues

---
 btor.ys | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'btor.ys')

diff --git a/btor.ys b/btor.ys
index 5293ed63b..65accc95c 100644
--- a/btor.ys
+++ b/btor.ys
@@ -1,4 +1,6 @@
 #design should be loaded before executing 
+#set the: hierarchy -top <module_top>
+#set the: hierarchy -libdir <dir>
 
 #high level synthesis
 #################
@@ -7,13 +9,12 @@ proc;
 opt; opt_const -mux_undef; opt;
 rename -hide;;;
 #converting pmux to mux
-techmap -map techlibs/common/pmux2mux.v;
-opt;
-#converting asyn memory write to syn memory
-memory_dff; 
-opt;
+techmap -map techlibs/common/pmux2mux.v;;
+memory -nomap;;
 #flatten design
-flatten;;;
+flatten;;
+#converting asyn memory write to syn memory
+memory_unpack; 
 #cell output to be a single wire
 splitnets -driver;
 opt;;;
-- 
cgit v1.2.3


From 234d0d0e1c316d7253c56c522dcc982a5e6049a1 Mon Sep 17 00:00:00 2001
From: Ahmed Irfan <irfan@ubuntu.(none)>
Date: Sat, 18 Jan 2014 21:54:52 +0100
Subject: script added

---
 btor.ys | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

(limited to 'btor.ys')

diff --git a/btor.ys b/btor.ys
index 65accc95c..7f3882b57 100644
--- a/btor.ys
+++ b/btor.ys
@@ -1,10 +1,3 @@
-#design should be loaded before executing 
-#set the: hierarchy -top <module_top>
-#set the: hierarchy -libdir <dir>
-
-#high level synthesis
-#################
-#converting processes to cells
 proc; 
 opt; opt_const -mux_undef; opt;
 rename -hide;;;
@@ -17,6 +10,6 @@ flatten;;
 memory_unpack; 
 #cell output to be a single wire
 splitnets -driver;
+setundef -zero -undriven;
 opt;;;
-#writing btor
-write_btor design.btor;
+
-- 
cgit v1.2.3