From 9a689f33a56d4b351bab021989f79e9b19500c62 Mon Sep 17 00:00:00 2001
From: Ahmed Irfan <irfan@ubuntu.(none)>
Date: Fri, 17 Jan 2014 19:32:35 +0100
Subject: verilog default options pull shift operator width issues

---
 btor.ys | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'btor.ys')

diff --git a/btor.ys b/btor.ys
index 5293ed63b..65accc95c 100644
--- a/btor.ys
+++ b/btor.ys
@@ -1,4 +1,6 @@
 #design should be loaded before executing 
+#set the: hierarchy -top <module_top>
+#set the: hierarchy -libdir <dir>
 
 #high level synthesis
 #################
@@ -7,13 +9,12 @@ proc;
 opt; opt_const -mux_undef; opt;
 rename -hide;;;
 #converting pmux to mux
-techmap -map techlibs/common/pmux2mux.v;
-opt;
-#converting asyn memory write to syn memory
-memory_dff; 
-opt;
+techmap -map techlibs/common/pmux2mux.v;;
+memory -nomap;;
 #flatten design
-flatten;;;
+flatten;;
+#converting asyn memory write to syn memory
+memory_unpack; 
 #cell output to be a single wire
 splitnets -driver;
 opt;;;
-- 
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