From fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Mar 2020 12:57:01 -0700 Subject: kernel: use more ID::* --- backends/aiger/aiger.cc | 24 +++---- backends/aiger/xaiger.cc | 10 +-- backends/blif/blif.cc | 48 ++++++------- backends/btor/btor.cc | 102 +++++++++++++------------- backends/edif/edif.cc | 2 +- backends/firrtl/firrtl.cc | 46 ++++++------ backends/simplec/simplec.cc | 30 ++++---- backends/smt2/smt2.cc | 74 +++++++++---------- backends/smv/smv.cc | 140 ++++++++++++++++++------------------ backends/spice/spice.cc | 2 +- backends/verilog/verilog_backend.cc | 82 ++++++++++----------- 11 files changed, 280 insertions(+), 280 deletions(-) (limited to 'backends') diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index a51e3648c..25f584f95 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -171,8 +171,8 @@ struct AigerWriter { if (cell->type == "$_NOT_") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); undriven_bits.erase(Y); not_map[Y] = A; @@ -191,9 +191,9 @@ struct AigerWriter if (cell->type == "$_AND_") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit B = sigmap(cell->getPort("\\B").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit B = sigmap(cell->getPort(ID::B).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); unused_bits.erase(B); undriven_bits.erase(Y); @@ -203,7 +203,7 @@ struct AigerWriter if (cell->type == "$initstate") { - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); undriven_bits.erase(Y); initstate_bits.insert(Y); continue; @@ -211,7 +211,7 @@ struct AigerWriter if (cell->type == "$assert") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); unused_bits.erase(A); unused_bits.erase(EN); @@ -221,7 +221,7 @@ struct AigerWriter if (cell->type == "$assume") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); unused_bits.erase(A); unused_bits.erase(EN); @@ -231,7 +231,7 @@ struct AigerWriter if (cell->type == "$live") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); unused_bits.erase(A); unused_bits.erase(EN); @@ -241,7 +241,7 @@ struct AigerWriter if (cell->type == "$fair") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); unused_bits.erase(A); unused_bits.erase(EN); @@ -251,7 +251,7 @@ struct AigerWriter if (cell->type == "$anyconst") { - for (auto bit : sigmap(cell->getPort("\\Y"))) { + for (auto bit : sigmap(cell->getPort(ID::Y))) { undriven_bits.erase(bit); ff_map[bit] = bit; } @@ -260,7 +260,7 @@ struct AigerWriter if (cell->type == "$anyseq") { - for (auto bit : sigmap(cell->getPort("\\Y"))) { + for (auto bit : sigmap(cell->getPort(ID::Y))) { undriven_bits.erase(bit); input_bits.insert(bit); } diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cde6d066a..fe1a6446b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -192,8 +192,8 @@ struct XAigerWriter if (!cell->has_keep_attr()) { if (cell->type == "$_NOT_") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); undriven_bits.erase(Y); not_map[Y] = A; @@ -202,9 +202,9 @@ struct XAigerWriter if (cell->type == "$_AND_") { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit B = sigmap(cell->getPort("\\B").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit B = sigmap(cell->getPort(ID::B).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); unused_bits.erase(B); undriven_bits.erase(Y); diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 4bdaf7a7f..4573d488c 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -239,95 +239,95 @@ struct BlifDumper if (!config->icells_mode && cell->type == "$_NOT_") { f << stringf(".names %s %s\n0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_AND_") { f << stringf(".names %s %s %s\n11 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_OR_") { f << stringf(".names %s %s %s\n1- 1\n-1 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_XOR_") { f << stringf(".names %s %s %s\n10 1\n01 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_NAND_") { f << stringf(".names %s %s %s\n0- 1\n-0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_NOR_") { f << stringf(".names %s %s %s\n00 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_XNOR_") { f << stringf(".names %s %s %s\n11 1\n00 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_ANDNOT_") { f << stringf(".names %s %s %s\n10 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_ORNOT_") { f << stringf(".names %s %s %s\n1- 1\n-0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_AOI3_") { f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort("\\C")), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_OAI3_") { f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort("\\C")), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_AOI4_") { f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), - cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), + cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_OAI4_") { f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), - cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), + cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_MUX_") { f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), - cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), + cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y))); goto internal_cell; } if (!config->icells_mode && cell->type == "$_NMUX_") { f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), - cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), + cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y))); goto internal_cell; } @@ -363,12 +363,12 @@ struct BlifDumper if (!config->icells_mode && cell->type == "$lut") { f << stringf(".names"); - auto &inputs = cell->getPort("\\A"); + auto &inputs = cell->getPort(ID::A); auto width = cell->parameters.at("\\WIDTH").as_int(); log_assert(inputs.size() == width); for (int i = width-1; i >= 0; i--) f << stringf(" %s", cstr(inputs.extract(i, 1))); - auto &output = cell->getPort("\\Y"); + auto &output = cell->getPort(ID::Y); log_assert(output.size() == 1); f << stringf(" %s", cstr(output)); f << stringf("\n"); @@ -385,7 +385,7 @@ struct BlifDumper if (!config->icells_mode && cell->type == "$sop") { f << stringf(".names"); - auto &inputs = cell->getPort("\\A"); + auto &inputs = cell->getPort(ID::A); auto width = cell->parameters.at("\\WIDTH").as_int(); auto depth = cell->parameters.at("\\DEPTH").as_int(); vector table = cell->parameters.at("\\TABLE").bits; @@ -394,7 +394,7 @@ struct BlifDumper log_assert(inputs.size() == width); for (int i = 0; i < width; i++) f << stringf(" %s", cstr(inputs.extract(i, 1))); - auto &output = cell->getPort("\\Y"); + auto &output = cell->getPort(ID::Y); log_assert(output.size() == 1); f << stringf(" %s", cstr(output)); f << stringf("\n"); @@ -647,7 +647,7 @@ struct BlifBackend : public Backend { if (top_module_name.empty()) for (auto module : design->modules()) - if (module->get_bool_attribute("\\top")) + if (module->get_bool_attribute(ID::top)) top_module_name = module->name.str(); *f << stringf("# Generated by %s\n", yosys_version_str); diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index e68a6a08f..d2bca8cd6 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -203,9 +203,9 @@ struct BtorWorker if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor"; log_assert(!btor_op.empty()); - int width = GetSize(cell->getPort("\\Y")); - width = std::max(width, GetSize(cell->getPort("\\A"))); - width = std::max(width, GetSize(cell->getPort("\\B"))); + int width = GetSize(cell->getPort(ID::Y)); + width = std::max(width, GetSize(cell->getPort(ID::A))); + width = std::max(width, GetSize(cell->getPort(ID::B))); bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; @@ -224,8 +224,8 @@ struct BtorWorker if (btor_op == "shift") { - int nid_a = get_sig_nid(cell->getPort("\\A"), width, false); - int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, false); + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); int nid_r = next_nid++; btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b); @@ -246,14 +246,14 @@ struct BtorWorker } else { - int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed); - int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); nid = next_nid++; btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) < width) { int sid = get_bv_sid(GetSize(sig)); @@ -273,21 +273,21 @@ struct BtorWorker if (cell->type == "$mod") btor_op = "rem"; log_assert(!btor_op.empty()); - int width = GetSize(cell->getPort("\\Y")); - width = std::max(width, GetSize(cell->getPort("\\A"))); - width = std::max(width, GetSize(cell->getPort("\\B"))); + int width = GetSize(cell->getPort(ID::Y)); + width = std::max(width, GetSize(cell->getPort(ID::A))); + width = std::max(width, GetSize(cell->getPort(ID::B))); bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; - int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed); - int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); int sid = get_bv_sid(width); int nid = next_nid++; btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) < width) { int sid = get_bv_sid(GetSize(sig)); @@ -303,8 +303,8 @@ struct BtorWorker if (cell->type.in("$_ANDNOT_", "$_ORNOT_")) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_b = get_sig_nid(cell->getPort("\\B")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_b = get_sig_nid(cell->getPort(ID::B)); int nid1 = next_nid++; int nid2 = next_nid++; @@ -319,7 +319,7 @@ struct BtorWorker btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); add_nid_sig(nid2, sig); goto okay; } @@ -327,8 +327,8 @@ struct BtorWorker if (cell->type.in("$_OAI3_", "$_AOI3_")) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_b = get_sig_nid(cell->getPort("\\B")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_b = get_sig_nid(cell->getPort(ID::B)); int nid_c = get_sig_nid(cell->getPort("\\C")); int nid1 = next_nid++; @@ -347,7 +347,7 @@ struct BtorWorker btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); add_nid_sig(nid3, sig); goto okay; } @@ -355,8 +355,8 @@ struct BtorWorker if (cell->type.in("$_OAI4_", "$_AOI4_")) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_b = get_sig_nid(cell->getPort("\\B")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_b = get_sig_nid(cell->getPort(ID::B)); int nid_c = get_sig_nid(cell->getPort("\\C")); int nid_d = get_sig_nid(cell->getPort("\\D")); @@ -379,7 +379,7 @@ struct BtorWorker btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); add_nid_sig(nid4, sig); goto okay; } @@ -396,15 +396,15 @@ struct BtorWorker log_assert(!btor_op.empty()); int width = 1; - width = std::max(width, GetSize(cell->getPort("\\A"))); - width = std::max(width, GetSize(cell->getPort("\\B"))); + width = std::max(width, GetSize(cell->getPort(ID::A))); + width = std::max(width, GetSize(cell->getPort(ID::B))); bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed); - int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); int nid = next_nid++; if (cell->type.in("$lt", "$le", "$ge", "$gt")) { @@ -413,7 +413,7 @@ struct BtorWorker btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -433,18 +433,18 @@ struct BtorWorker if (cell->type == "$neg") btor_op = "neg"; log_assert(!btor_op.empty()); - int width = GetSize(cell->getPort("\\Y")); - width = std::max(width, GetSize(cell->getPort("\\A"))); + int width = GetSize(cell->getPort(ID::Y)); + width = std::max(width, GetSize(cell->getPort(ID::A))); bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; int sid = get_bv_sid(width); - int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); int nid = next_nid++; btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) < width) { int sid = get_bv_sid(GetSize(sig)); @@ -466,16 +466,16 @@ struct BtorWorker log_assert(!btor_op.empty()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort("\\B")) : 0; + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0; - if (GetSize(cell->getPort("\\A")) > 1) { + if (GetSize(cell->getPort(ID::A)) > 1) { int nid_red_a = next_nid++; btorf("%d redor %d %d\n", nid_red_a, sid, nid_a); nid_a = nid_red_a; } - if (btor_op != "not" && GetSize(cell->getPort("\\B")) > 1) { + if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) { int nid_red_b = next_nid++; btorf("%d redor %d %d\n", nid_red_b, sid, nid_b); nid_b = nid_red_b; @@ -487,7 +487,7 @@ struct BtorWorker else btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -510,7 +510,7 @@ struct BtorWorker log_assert(!btor_op.empty()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid = next_nid++; @@ -523,7 +523,7 @@ struct BtorWorker btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -539,10 +539,10 @@ struct BtorWorker if (cell->type.in("$mux", "$_MUX_", "$_NMUX_")) { - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); int nid_a = get_sig_nid(sig_a); int nid_b = get_sig_nid(sig_b); @@ -566,10 +566,10 @@ struct BtorWorker if (cell->type == "$pmux") { - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); int width = GetSize(sig_a); int sid = get_bv_sid(width); @@ -654,7 +654,7 @@ struct BtorWorker if (cell->type.in("$anyconst", "$anyseq")) { - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); int sid = get_bv_sid(GetSize(sig_y)); int nid = next_nid++; @@ -672,7 +672,7 @@ struct BtorWorker if (cell->type == "$initstate") { - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); if (initstate_nid < 0) { @@ -1104,7 +1104,7 @@ struct BtorWorker btorf_push(log_id(cell)); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid_en = get_sig_nid(cell->getPort("\\EN")); int nid_not_en = next_nid++; int nid_a_or_not_en = next_nid++; @@ -1122,7 +1122,7 @@ struct BtorWorker btorf_push(log_id(cell)); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid_en = get_sig_nid(cell->getPort("\\EN")); int nid_not_a = next_nid++; int nid_en_and_not_a = next_nid++; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index cb1b4c284..cc20f17fc 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -172,7 +172,7 @@ struct EdifBackend : public Backend { if (top_module_name.empty()) for (auto module : design->modules()) - if (module->get_bool_attribute("\\top")) + if (module->get_bool_attribute(ID::top)) top_module_name = module->name.str(); for (auto module : design->modules()) diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 22aa686a7..79445a61c 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -199,7 +199,7 @@ struct FirrtlWorker const char *atLine() { if (srcLine == "") { if (pCell) { - auto p = pCell->attributes.find("\\src"); + auto p = pCell->attributes.find(ID::src); srcLine = " at " + p->second.decode_string(); } } @@ -444,7 +444,7 @@ struct FirrtlWorker if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor")) { - string a_expr = make_expr(cell->getPort("\\A")); + string a_expr = make_expr(cell->getPort(ID::A)); wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); if (a_signed) { @@ -486,7 +486,7 @@ struct FirrtlWorker expr = stringf("asUInt(%s)", expr.c_str()); cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } @@ -494,8 +494,8 @@ struct FirrtlWorker "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl", "$logic_and", "$logic_or", "$pow")) { - string a_expr = make_expr(cell->getPort("\\A")); - string b_expr = make_expr(cell->getPort("\\B")); + string a_expr = make_expr(cell->getPort(ID::A)); + string b_expr = make_expr(cell->getPort(ID::B)); wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); if (a_signed) { @@ -532,7 +532,7 @@ struct FirrtlWorker } // Assume the FIRRTL width is the width of "A" firrtl_width = a_width; - auto a_sig = cell->getPort("\\A"); + auto a_sig = cell->getPort(ID::A); if (cell->type == "$add") { primop = "add"; @@ -610,7 +610,7 @@ struct FirrtlWorker // We'll need to offset this by extracting the un-widened portion as Verilog would do. extract_y_bits = true; // Is the shift amount constant? - auto b_sig = cell->getPort("\\B"); + auto b_sig = cell->getPort(ID::B); if (b_sig.is_fully_const()) { primop = "shl"; int shift_amount = b_sig.as_int(); @@ -627,7 +627,7 @@ struct FirrtlWorker // We don't need to extract a specific range of bits. extract_y_bits = false; // Is the shift amount constant? - auto b_sig = cell->getPort("\\B"); + auto b_sig = cell->getPort(ID::B); if (b_sig.is_fully_const()) { primop = "shr"; int shift_amount = b_sig.as_int(); @@ -669,7 +669,7 @@ struct FirrtlWorker a_expr = firrtl_is_signed ? "SInt(1)" : "UInt(1)"; extract_y_bits = true; // Is the shift amount constant? - auto b_sig = cell->getPort("\\B"); + auto b_sig = cell->getPort(ID::B); if (b_sig.is_fully_const()) { primop = "shl"; int shiftAmount = b_sig.as_int(); @@ -713,7 +713,7 @@ struct FirrtlWorker expr = stringf("asUInt(%s)", expr.c_str()); cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } @@ -721,15 +721,15 @@ struct FirrtlWorker if (cell->type.in("$mux")) { int width = cell->parameters.at("\\WIDTH").as_int(); - string a_expr = make_expr(cell->getPort("\\A")); - string b_expr = make_expr(cell->getPort("\\B")); - string s_expr = make_expr(cell->getPort("\\S")); + string a_expr = make_expr(cell->getPort(ID::A)); + string b_expr = make_expr(cell->getPort(ID::B)); + string s_expr = make_expr(cell->getPort(ID::S)); wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), width)); string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str()); cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } @@ -885,9 +885,9 @@ struct FirrtlWorker // assign y = a[b +: y_width]; // We'll extract the correct bits as part of the primop. - string a_expr = make_expr(cell->getPort("\\A")); + string a_expr = make_expr(cell->getPort(ID::A)); // Get the initial bit selector - string b_expr = make_expr(cell->getPort("\\B")); + string b_expr = make_expr(cell->getPort(ID::B)); wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); if (cell->getParam("\\B_SIGNED").as_bool()) { @@ -899,15 +899,15 @@ struct FirrtlWorker string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str()); cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } if (cell->type == "$shift") { // assign y = a >> b; // where b may be negative - string a_expr = make_expr(cell->getPort("\\A")); - string b_expr = make_expr(cell->getPort("\\B")); + string a_expr = make_expr(cell->getPort(ID::A)); + string b_expr = make_expr(cell->getPort(ID::B)); auto b_string = b_expr.c_str(); string expr; wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); @@ -925,13 +925,13 @@ struct FirrtlWorker expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string); } cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } if (cell->type == "$pos") { // assign y = a; // printCell(cell); - string a_expr = make_expr(cell->getPort("\\A")); + string a_expr = make_expr(cell->getPort(ID::A)); // Verilog appears to treat the result as signed, so if the result is wider than "A", // we need to pad. if (a_width < y_width) { @@ -939,7 +939,7 @@ struct FirrtlWorker } wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), a_expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell)); @@ -1112,7 +1112,7 @@ struct FirrtlBackend : public Backend { for (auto module : design->modules()) { make_id(module->name); last = module; - if (top == nullptr && module->get_bool_attribute("\\top")) { + if (top == nullptr && module->get_bool_attribute(ID::top)) { top = module; } for (auto wire : module->wires()) diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index 54dbb84af..bdcc2a791 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -380,8 +380,8 @@ struct SimplecWorker { if (cell->type.in("$_BUF_", "$_NOT_")) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string expr; @@ -399,9 +399,9 @@ struct SimplecWorker if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit b = sigmaps.at(work->module)(cell->getPort("\\B")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; @@ -426,10 +426,10 @@ struct SimplecWorker if (cell->type.in("$_AOI3_", "$_OAI3_")) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit b = sigmaps.at(work->module)(cell->getPort("\\B")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); SigBit c = sigmaps.at(work->module)(cell->getPort("\\C")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; @@ -449,11 +449,11 @@ struct SimplecWorker if (cell->type.in("$_AOI4_", "$_OAI4_")) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit b = sigmaps.at(work->module)(cell->getPort("\\B")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); SigBit c = sigmaps.at(work->module)(cell->getPort("\\C")); SigBit d = sigmaps.at(work->module)(cell->getPort("\\D")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; @@ -474,10 +474,10 @@ struct SimplecWorker if (cell->type.in("$_MUX_", "$_NMUX_")) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit b = sigmaps.at(work->module)(cell->getPort("\\B")); - SigBit s = sigmaps.at(work->module)(cell->getPort("\\S")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); + SigBit s = sigmaps.at(work->module)(cell->getPort(ID::S)); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index eb4826051..e1d6f5535 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -367,15 +367,15 @@ struct Smt2Worker void export_gate(RTLIL::Cell *cell, std::string expr) { - RTLIL::SigBit bit = sigmap(cell->getPort("\\Y").as_bit()); + RTLIL::SigBit bit = sigmap(cell->getPort(ID::Y).as_bit()); std::string processed_expr; for (char ch : expr) { - if (ch == 'A') processed_expr += get_bool(cell->getPort("\\A")); - else if (ch == 'B') processed_expr += get_bool(cell->getPort("\\B")); + if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A)); + else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B)); else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C")); else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D")); - else if (ch == 'S') processed_expr += get_bool(cell->getPort("\\S")); + else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S)); else processed_expr += ch; } @@ -391,23 +391,23 @@ struct Smt2Worker void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0) { RTLIL::SigSpec sig_a, sig_b; - RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); + RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); int width = GetSize(sig_y); if (type == 's' || type == 'd' || type == 'b') { - width = max(width, GetSize(cell->getPort("\\A"))); - if (cell->hasPort("\\B")) - width = max(width, GetSize(cell->getPort("\\B"))); + width = max(width, GetSize(cell->getPort(ID::A))); + if (cell->hasPort(ID::B)) + width = max(width, GetSize(cell->getPort(ID::B))); } - if (cell->hasPort("\\A")) { - sig_a = cell->getPort("\\A"); + if (cell->hasPort(ID::A)) { + sig_a = cell->getPort(ID::A); sig_a.extend_u0(width, is_signed); } - if (cell->hasPort("\\B")) { - sig_b = cell->getPort("\\B"); + if (cell->hasPort(ID::B)) { + sig_b = cell->getPort(ID::B); sig_b.extend_u0(width, is_signed && !(type == 's')); } @@ -416,7 +416,7 @@ struct Smt2Worker for (char ch : expr) { if (ch == 'A') processed_expr += get_bv(sig_a); else if (ch == 'B') processed_expr += get_bv(sig_b); - else if (ch == 'P') processed_expr += get_bv(cell->getPort("\\B")); + else if (ch == 'P') processed_expr += get_bv(cell->getPort(ID::B)); else if (ch == 'L') processed_expr += is_signed ? "a" : "l"; else if (ch == 'U') processed_expr += is_signed ? "s" : "u"; else processed_expr += ch; @@ -443,7 +443,7 @@ struct Smt2Worker void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val) { - RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); + RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); std::string processed_expr; for (char ch : expr) @@ -482,7 +482,7 @@ struct Smt2Worker if (cell->type == "$initstate") { - SigBit bit = sigmap(cell->getPort("\\Y").as_bit()); + SigBit bit = sigmap(cell->getPort(ID::Y).as_bit()); decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n", get_id(module), idcounter, get_id(module), get_id(module), log_signal(bit))); register_bool(bit, idcounter++); @@ -532,22 +532,22 @@ struct Smt2Worker if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) { registers.insert(cell); - string infostr = cell->attributes.count("\\src") ? cell->attributes.at("\\src").decode_string().c_str() : get_id(cell); + string infostr = cell->attributes.count(ID::src) ? cell->attributes.at(ID::src).decode_string().c_str() : get_id(cell); if (cell->attributes.count("\\reg")) infostr += " " + cell->attributes.at("\\reg").decode_string(); - decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort("\\Y")), infostr.c_str())); - if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\maximize")){ + decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(ID::Y)), infostr.c_str())); + if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\maximize")){ decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter)); - log("Wire %s is maximized\n", cell->getPort("\\Y").as_wire()->name.str().c_str()); + log("Wire %s is maximized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str()); } - else if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\minimize")){ + else if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\minimize")){ decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter)); - log("Wire %s is minimized\n", cell->getPort("\\Y").as_wire()->name.str().c_str()); + log("Wire %s is minimized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str()); } - makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y"))); + makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::Y))); if (cell->type == "$anyseq") ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter)); - register_bv(cell->getPort("\\Y"), idcounter++); + register_bv(cell->getPort(ID::Y), idcounter++); recursive_cells.erase(cell); return; } @@ -566,7 +566,7 @@ struct Smt2Worker if (cell->getParam("\\B_SIGNED").as_bool()) { return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) " "(bvlshr A B) (bvlshr A (bvneg B)))", - GetSize(cell->getPort("\\B")), 0), 's'); + GetSize(cell->getPort(ID::B)), 0), 's'); } else { return export_bvop(cell, "(bvlshr A B)", 's'); } @@ -593,9 +593,9 @@ struct Smt2Worker if (cell->type == "$mod") return export_bvop(cell, "(bvUrem A B)", 'd'); if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool") && - 2*GetSize(cell->getPort("\\A").chunks()) < GetSize(cell->getPort("\\A"))) { + 2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) { bool is_and = cell->type == "$reduce_and"; - string bits(GetSize(cell->getPort("\\A")), is_and ? '1' : '0'); + string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0'); return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b'); } @@ -611,11 +611,11 @@ struct Smt2Worker if (cell->type.in("$mux", "$pmux")) { - int width = GetSize(cell->getPort("\\Y")); - std::string processed_expr = get_bv(cell->getPort("\\A")); + int width = GetSize(cell->getPort(ID::Y)); + std::string processed_expr = get_bv(cell->getPort(ID::A)); - RTLIL::SigSpec sig_b = cell->getPort("\\B"); - RTLIL::SigSpec sig_s = cell->getPort("\\S"); + RTLIL::SigSpec sig_b = cell->getPort(ID::B); + RTLIL::SigSpec sig_s = cell->getPort(ID::S); get_bv(sig_b); get_bv(sig_s); @@ -626,7 +626,7 @@ struct Smt2Worker if (verbose) log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell)); - RTLIL::SigSpec sig = sigmap(cell->getPort("\\Y")); + RTLIL::SigSpec sig = sigmap(cell->getPort(ID::Y)); decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n", get_id(module), idcounter, get_id(module), width, processed_expr.c_str(), log_signal(sig))); register_bv(sig, idcounter++); @@ -895,9 +895,9 @@ struct Smt2Worker cell->type == "$assume" ? 'u' : cell->type == "$cover" ? 'c' : 0; - string name_a = get_bool(cell->getPort("\\A")); + string name_a = get_bool(cell->getPort(ID::A)); string name_en = get_bool(cell->getPort("\\EN")); - string infostr = (cell->name[0] == '$' && cell->attributes.count("\\src")) ? cell->attributes.at("\\src").decode_string() : get_id(cell); + string infostr = (cell->name[0] == '$' && cell->attributes.count(ID::src)) ? cell->attributes.at(ID::src).decode_string() : get_id(cell); decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str())); if (cell->type == "$cover") @@ -983,11 +983,11 @@ struct Smt2Worker if (cell->type.in("$anyconst", "$allconst")) { - std::string expr_d = get_bv(cell->getPort("\\Y")); - std::string expr_q = get_bv(cell->getPort("\\Y"), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Y")))); + std::string expr_d = get_bv(cell->getPort(ID::Y)); + std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state"); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Y)))); if (cell->type == "$anyconst") - ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Y")).c_str(), get_bv(cell->getPort("\\Y"), "other_state").c_str())); + ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str())); } if (cell->type == "$mem") diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index f755307bf..39170ebf9 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -229,7 +229,7 @@ struct SmvWorker if (cell->type.in("$assert")) { - SigSpec sig_a = cell->getPort("\\A"); + SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_en = cell->getPort("\\EN"); invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a))); @@ -239,10 +239,10 @@ struct SmvWorker if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) { - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_b = cell->getPort("\\B"); + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_b = cell->getPort(ID::B); - int width_y = GetSize(cell->getPort("\\Y")); + int width_y = GetSize(cell->getPort(ID::Y)); int shift_b_width = GetSize(sig_b); int width_ay = max(GetSize(sig_a), width_y); int width = width_ay; @@ -303,14 +303,14 @@ struct SmvWorker GetSize(sig_b)-shift_b_width, width_y, expr.c_str()); } - definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str())); + definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr.c_str())); continue; } if (cell->type.in("$not", "$pos", "$neg")) { - int width = GetSize(cell->getPort("\\Y")); + int width = GetSize(cell->getPort(ID::Y)); string expr_a, op; if (cell->type == "$not") op = "!"; @@ -319,13 +319,13 @@ struct SmvWorker if (cell->getParam("\\A_SIGNED").as_bool()) { - definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort("\\Y")), - op.c_str(), rvalue_s(cell->getPort("\\A"), width))); + definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)), + op.c_str(), rvalue_s(cell->getPort(ID::A), width))); } else { - definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), - op.c_str(), rvalue_u(cell->getPort("\\A"), width))); + definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), + op.c_str(), rvalue_u(cell->getPort(ID::A), width))); } continue; @@ -333,7 +333,7 @@ struct SmvWorker if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor")) { - int width = GetSize(cell->getPort("\\Y")); + int width = GetSize(cell->getPort(ID::Y)); string expr_a, expr_b, op; if (cell->type == "$add") op = "+"; @@ -346,13 +346,13 @@ struct SmvWorker if (cell->getParam("\\A_SIGNED").as_bool()) { - definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort("\\Y")), - rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width))); + definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)), + rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width))); } else { - definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")), - rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width))); + definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)), + rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width))); } continue; @@ -360,9 +360,9 @@ struct SmvWorker if (cell->type.in("$div", "$mod")) { - int width_y = GetSize(cell->getPort("\\Y")); - int width = max(width_y, GetSize(cell->getPort("\\A"))); - width = max(width, GetSize(cell->getPort("\\B"))); + int width_y = GetSize(cell->getPort(ID::Y)); + int width = max(width_y, GetSize(cell->getPort(ID::A))); + width = max(width, GetSize(cell->getPort(ID::B))); string expr_a, expr_b, op; if (cell->type == "$div") op = "/"; @@ -370,13 +370,13 @@ struct SmvWorker if (cell->getParam("\\A_SIGNED").as_bool()) { - definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort("\\Y")), - rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width), width_y)); + definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)), + rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y)); } else { - definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort("\\Y")), - rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width), width_y)); + definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(ID::Y)), + rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width), width_y)); } continue; @@ -384,7 +384,7 @@ struct SmvWorker if (cell->type.in("$eq", "$ne", "$eqx", "$nex", "$lt", "$le", "$ge", "$gt")) { - int width = max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B"))); + int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B))); string expr_a, expr_b, op; if (cell->type == "$eq") op = "="; @@ -398,27 +398,27 @@ struct SmvWorker if (cell->getParam("\\A_SIGNED").as_bool()) { - expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\A")), width); - expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\B")), width); + expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width); + expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width); } else { - expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort("\\A")), width); - expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort("\\B")), width); + expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::A)), width); + expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::B)), width); } - definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort("\\Y")), - expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort("\\Y")))); + definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)), + expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(ID::Y)))); continue; } if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) { - int width_a = GetSize(cell->getPort("\\A")); - int width_y = GetSize(cell->getPort("\\Y")); - const char *expr_a = rvalue(cell->getPort("\\A")); - const char *expr_y = lvalue(cell->getPort("\\Y")); + int width_a = GetSize(cell->getPort(ID::A)); + int width_y = GetSize(cell->getPort(ID::Y)); + const char *expr_a = rvalue(cell->getPort(ID::A)); + const char *expr_y = lvalue(cell->getPort(ID::Y)); string expr; if (cell->type == "$reduce_and") expr = stringf("%s = !0ub%d_0", expr_a, width_a); @@ -431,11 +431,11 @@ struct SmvWorker if (cell->type.in("$reduce_xor", "$reduce_xnor")) { - int width_y = GetSize(cell->getPort("\\Y")); - const char *expr_y = lvalue(cell->getPort("\\Y")); + int width_y = GetSize(cell->getPort(ID::Y)); + const char *expr_y = lvalue(cell->getPort(ID::Y)); string expr; - for (auto bit : cell->getPort("\\A")) { + for (auto bit : cell->getPort(ID::A)) { if (!expr.empty()) expr += " xor "; expr += rvalue(bit); @@ -450,13 +450,13 @@ struct SmvWorker if (cell->type.in("$logic_and", "$logic_or")) { - int width_a = GetSize(cell->getPort("\\A")); - int width_b = GetSize(cell->getPort("\\B")); - int width_y = GetSize(cell->getPort("\\Y")); + int width_a = GetSize(cell->getPort(ID::A)); + int width_b = GetSize(cell->getPort(ID::B)); + int width_y = GetSize(cell->getPort(ID::Y)); - string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort("\\A")), width_a); - string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort("\\B")), width_b); - const char *expr_y = lvalue(cell->getPort("\\Y")); + string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a); + string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::B)), width_b); + const char *expr_y = lvalue(cell->getPort(ID::Y)); string expr; if (cell->type == "$logic_and") expr = expr_a + " & " + expr_b; @@ -468,11 +468,11 @@ struct SmvWorker if (cell->type.in("$logic_not")) { - int width_a = GetSize(cell->getPort("\\A")); - int width_y = GetSize(cell->getPort("\\Y")); + int width_a = GetSize(cell->getPort(ID::A)); + int width_y = GetSize(cell->getPort(ID::Y)); - string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort("\\A")), width_a); - const char *expr_y = lvalue(cell->getPort("\\Y")); + string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a); + const char *expr_y = lvalue(cell->getPort(ID::Y)); definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a.c_str(), width_y)); continue; @@ -480,17 +480,17 @@ struct SmvWorker if (cell->type.in("$mux", "$pmux")) { - int width = GetSize(cell->getPort("\\Y")); - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_b = cell->getPort("\\B"); - SigSpec sig_s = cell->getPort("\\S"); + int width = GetSize(cell->getPort(ID::Y)); + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_b = cell->getPort(ID::B); + SigSpec sig_s = cell->getPort(ID::S); string expr; for (int i = 0; i < GetSize(sig_s); i++) expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width))); expr += rvalue(sig_a); - definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str())); + definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr.c_str())); continue; } @@ -504,7 +504,7 @@ struct SmvWorker if (cell->type.in("$_BUF_", "$_NOT_")) { string op = cell->type == "$_NOT_" ? "!" : ""; - definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), op.c_str(), rvalue(cell->getPort("\\A")))); + definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op.c_str(), rvalue(cell->getPort(ID::A)))); continue; } @@ -518,57 +518,57 @@ struct SmvWorker if (cell->type.in("$_XNOR_")) op = "xnor"; if (cell->type.in("$_ANDNOT_", "$_ORNOT_")) - definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B")))); + definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); else if (cell->type.in("$_NAND_", "$_NOR_")) - definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B")))); + definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); else - definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B")))); + definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); continue; } if (cell->type == "$_MUX_") { - definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\S")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\A")))); + definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A)))); continue; } if (cell->type == "$_NMUX_") { - definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\S")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\A")))); + definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A)))); continue; } if (cell->type == "$_AOI3_") { - definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")))); + definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")))); continue; } if (cell->type == "$_OAI3_") { - definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")))); + definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")))); continue; } if (cell->type == "$_AOI4_") { - definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D")))); + definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D")))); continue; } if (cell->type == "$_OAI4_") { - definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D")))); + definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D")))); continue; } diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 9b603a8c5..84e93b61b 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -201,7 +201,7 @@ struct SpiceBackend : public Backend { if (top_module_name.empty()) for (auto module : design->modules()) - if (module->get_bool_attribute("\\top")) + if (module->get_bool_attribute(ID::top)) top_module_name = module->name.str(); *f << stringf("* SPICE netlist generated by %s\n", yosys_version_str); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e0fd201e1..17bf8ee81 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -488,7 +488,7 @@ no_special_reg_name: void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", true); @@ -498,7 +498,7 @@ void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "A", true); f << stringf(" %s ", op.c_str()); @@ -511,7 +511,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) { if (cell->type == "$_NOT_") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); f << stringf("~"); dump_attributes(f, "", cell->attributes, ' '); @@ -522,7 +522,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) f << stringf("~("); @@ -547,7 +547,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_MUX_") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "S", false); f << stringf(" ? "); @@ -561,7 +561,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_NMUX_") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = !("); dump_cell_expr_port(f, cell, "S", false); f << stringf(" ? "); @@ -575,7 +575,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in("$_AOI3_", "$_OAI3_")) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); f << stringf(cell->type == "$_AOI3_" ? " & " : " | "); @@ -590,7 +590,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in("$_AOI4_", "$_OAI4_")) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); f << stringf(cell->type == "$_AOI4_" ? " & " : " | "); @@ -663,7 +663,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); dump_sigspec(f, cell->getPort("\\C")); f << stringf(" or %sedge ", pol_s == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->getPort("\\S")); + dump_sigspec(f, cell->getPort(ID::S)); f << stringf(" or %sedge ", pol_r == 'P' ? "pos" : "neg"); dump_sigspec(f, cell->getPort("\\R")); f << stringf(")\n"); @@ -674,7 +674,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); f << stringf("%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); - dump_sigspec(f, cell->getPort("\\S")); + dump_sigspec(f, cell->getPort(ID::S)); f << stringf(")\n"); f << stringf("%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); @@ -743,27 +743,27 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$shift") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); if (cell->getParam("\\B_SIGNED").as_bool()) { f << stringf("$signed("); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(")"); f << stringf(" < 0 ? "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" << - "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" : "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" >> "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); } else { - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" >> "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); } f << stringf(";\n"); return true; @@ -772,16 +772,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$shiftx") { std::string temp_id = next_auto_id(); - f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str()); - dump_sigspec(f, cell->getPort("\\A")); + f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str()); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(";\n"); f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = %s[", temp_id.c_str()); if (cell->getParam("\\B_SIGNED").as_bool()) f << stringf("$signed("); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); if (cell->getParam("\\B_SIGNED").as_bool()) f << stringf(")"); f << stringf(" +: %d", cell->getParam("\\Y_WIDTH").as_int()); @@ -792,14 +792,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_sigspec(f, cell->getPort("\\S")); + dump_sigspec(f, cell->getPort(ID::S)); f << stringf(" ? "); dump_attributes(f, "", cell->attributes, ' '); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" : "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(";\n"); return true; } @@ -807,7 +807,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$pmux") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->getPort("\\S").size(); + int s_width = cell->getPort(ID::S).size(); std::string func_name = cellname(cell); f << stringf("%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -839,13 +839,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "endfunction\n", indent.c_str()); f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = %s(", func_name.c_str()); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(", "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(", "); - dump_sigspec(f, cell->getPort("\\S")); + dump_sigspec(f, cell->getPort(ID::S)); f << stringf(");\n"); return true; } @@ -853,11 +853,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$tribuf") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_sigspec(f, cell->getPort("\\EN")); f << stringf(" ? "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int()); return true; } @@ -865,9 +865,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$slice") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); return true; } @@ -875,11 +875,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$concat") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = { "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" , "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" };\n"); return true; } @@ -887,12 +887,12 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$lut") { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_const(f, cell->parameters.at("\\LUT")); f << stringf(" >> "); dump_attributes(f, "", cell->attributes, ' '); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(";\n"); return true; } @@ -1324,7 +1324,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "always @* if (", indent.c_str()); dump_sigspec(f, cell->getPort("\\EN")); f << stringf(") %s(", cell->type.c_str()+1); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(");\n"); return true; } -- cgit v1.2.3