From b9cb483f3e2a498ee75a422e09164a920918362b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Sep 2014 21:20:59 +0200 Subject: Using $pos models for $bu0 --- backends/verilog/verilog_backend.cc | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'backends') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d1fa55b94..79672540b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -538,6 +538,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) HANDLE_UNIOP("$not", "~") HANDLE_UNIOP("$pos", "+") + HANDLE_UNIOP("$bu0", "+") HANDLE_UNIOP("$neg", "-") HANDLE_BINOP("$and", "&") @@ -651,22 +652,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == "$bu0") - { - f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); - if (cell->parameters["\\A_SIGNED"].as_bool()) { - f << stringf(" = $signed("); - dump_sigspec(f, cell->getPort("\\A")); - f << stringf(");\n"); - } else { - f << stringf(" = { 1'b0, "); - dump_sigspec(f, cell->getPort("\\A")); - f << stringf(" };\n"); - } - return true; - } - if (cell->type == "$concat") { f << stringf("%s" "assign ", indent.c_str()); -- cgit v1.2.3