From 9329a768181d3765a08c3b264c8b0031b732c0d4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 6 Sep 2014 20:30:46 +0200
Subject: Various bug fixes (related to $macc model testing)

---
 backends/verilog/verilog_backend.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'backends')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 82a2c519e..bbdbbbfaf 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -973,7 +973,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 			for (int i = 0; i < wire->width; i++)
 				if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
 					goto this_wire_aint_reg;
-			reg_wires.insert(wire->name);
+			if (wire->width)
+				reg_wires.insert(wire->name);
 		this_wire_aint_reg:;
 		}
 	}
-- 
cgit v1.2.3