From 861142923719aa84afc3bdf3c24a9a36e5d5fbaf Mon Sep 17 00:00:00 2001
From: Benjamin Barzen <bbarzen@barzen.io>
Date: Sun, 23 Apr 2023 01:24:36 +0200
Subject: ABC9: Cell Port Bug Patch (#3670)

* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
---
 backends/aiger/xaiger.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'backends')

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index e223f185e..68c2ff52f 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -274,6 +274,10 @@ struct XAigerWriter
 						continue;
 					auto offset = i.first.offset;
 
+					auto rhs = cell->getPort(i.first.name);
+					if (offset >= rhs.size())
+						continue;
+
 #ifndef NDEBUG
 					if (ys_debug(1)) {
 						static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
@@ -281,7 +285,7 @@ struct XAigerWriter
 								log_id(cell->type), log_id(i.first.name), offset, d);
 					}
 #endif
-					arrival_times[cell->getPort(i.first.name)[offset]] = d;
+					arrival_times[rhs[offset]] = d;
 				}
 
 				if (abc9_flop)
-- 
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