From 2d9484c12cd1fd96eca5253c876ad545ed209f40 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 15:40:28 -0700 Subject: When two boxes connect to each other, need not be a (* keep *) --- backends/aiger/xaiger.cc | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index fa6ba0aca..cbce4c83b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -405,12 +405,7 @@ struct XAigerWriter if (O != b) alias_map[O] = b; undriven_bits.erase(O); - - auto jt = input_bits.find(b); - if (jt != input_bits.end()) { - log_assert(keep_bits.count(O)); - input_bits.erase(b); - } + input_bits.erase(b); } } } -- cgit v1.2.3 From c340fbfab23c582103402bbd812d9bca4510dc41 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 21:58:04 -0700 Subject: Force $inout.out ports to begin with '$' to indicate internal --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cbce4c83b..21b281708 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -424,7 +424,7 @@ struct XAigerWriter // inherit existing inout's drivers if ((wire->port_input && wire->port_output && !undriven_bits.count(bit)) || keep_bits.count(bit)) { - RTLIL::IdString wire_name = wire->name.str() + "$inout.out"; + RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str()); RTLIL::Wire *new_wire = module->wire(wire_name); if (!new_wire) new_wire = module->addWire(wire_name, GetSize(wire)); -- cgit v1.2.3 From 44374b1b2b0dbc455c9e43d713e133d7d78a5e1a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 21:58:40 -0700 Subject: "abc_padding" attr for blackbox outputs that were padded, remove them later --- backends/aiger/xaiger.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 21b281708..5e49f3c80 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -350,6 +350,8 @@ struct XAigerWriter if (!box_module || !box_module->attributes.count("\\abc_box_id")) continue; + bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); + // Fully pad all unused input connections of this box cell with S0 // Fully pad all undriven output connections of this box cell with anonymous wires // NB: Assume box_module->ports are sorted alphabetically @@ -394,7 +396,10 @@ struct XAigerWriter rhs = it->second; } else { - rhs = module->addWire(NEW_ID, GetSize(w)); + Wire *wire = module->addWire(NEW_ID, GetSize(w)); + if (blackbox) + wire->set_bool_attribute(ID(abc_padding)); + rhs = wire; cell->setPort(port_name, rhs); } -- cgit v1.2.3