From 369bf81a7049c96f62af084bb5007fbf45e36ab4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 27 Dec 2013 14:20:15 +0100 Subject: Added support for non-const === and !== (for miter circuits) --- backends/verilog/verilog_backend.cc | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'backends') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index ff41c2e3c..d8160c97b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -506,12 +506,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) HANDLE_BINOP("$sshl", "<<<") HANDLE_BINOP("$sshr", ">>>") - HANDLE_BINOP("$lt", "<") - HANDLE_BINOP("$le", "<=") - HANDLE_BINOP("$eq", "==") - HANDLE_BINOP("$ne", "!=") - HANDLE_BINOP("$ge", ">=") - HANDLE_BINOP("$gt", ">") + HANDLE_BINOP("$lt", "<") + HANDLE_BINOP("$le", "<=") + HANDLE_BINOP("$eq", "==") + HANDLE_BINOP("$ne", "!=") + HANDLE_BINOP("$eqx", "===") + HANDLE_BINOP("$nex", "!==") + HANDLE_BINOP("$ge", ">=") + HANDLE_BINOP("$gt", ">") HANDLE_BINOP("$add", "+") HANDLE_BINOP("$sub", "-") -- cgit v1.2.3 From 74d0de3b74cdf5d41eacd588d69488290549fd7e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 28 Dec 2013 12:14:47 +0100 Subject: Updated manual/command-reference-manual.tex --- backends/ilang/ilang_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends') diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 66775b2a5..924e316bc 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -402,7 +402,7 @@ struct DumpPass : public Pass { log("ilang format.\n"); log("\n"); log(" -m\n"); - log(" also dump the module headers, even if only parts of a single"); + log(" also dump the module headers, even if only parts of a single\n"); log(" module is selected\n"); log("\n"); log(" -n\n"); -- cgit v1.2.3