From 0aad88a2fb23e5481538122e1bd4c0fac9ba5e90 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 11 Dec 2021 16:07:29 +0100
Subject: Add clean_zerowidth pass, use it for Verilog output.

This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
---
 backends/verilog/verilog_backend.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 13c78c526..e4781ef3e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2300,6 +2300,8 @@ struct VerilogBackend : public Backend {
 			extmem_prefix = filename.substr(0, filename.rfind('.'));
 		}
 
+		Pass::call(design, "clean_zerowidth");
+
 		design->sort();
 
 		*f << stringf("/* Generated by %s */\n", yosys_version_str);
-- 
cgit v1.2.3