From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- backends/spice/spice.cc | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index e7926e90e..c7f832c64 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -27,16 +27,16 @@ static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { - log_assert(s.chunks.size() == 1 && s.chunks[0].width == 1); - if (s.chunks[0].wire) { - if (s.chunks[0].wire->width > 1) - fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks[0].wire->name), s.chunks[0].offset); + log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1); + if (s.__chunks[0].wire) { + if (s.__chunks[0].wire->width > 1) + fprintf(f, " %s[%d]", RTLIL::id2cstr(s.__chunks[0].wire->name), s.__chunks[0].offset); else - fprintf(f, " %s", RTLIL::id2cstr(s.chunks[0].wire->name)); + fprintf(f, " %s", RTLIL::id2cstr(s.__chunks[0].wire->name)); } else { - if (s.chunks[0].data.bits.at(0) == RTLIL::State::S0) + if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S0) fprintf(f, " %s", neg.c_str()); - else if (s.chunks[0].data.bits.at(0) == RTLIL::State::S1) + else if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S1) fprintf(f, " %s", pos.c_str()); else fprintf(f, " %s%d", ncpf.c_str(), nc_counter++); @@ -90,9 +90,9 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de } for (auto &sig : port_sigs) { - for (int i = 0; i < sig.width; i++) { - RTLIL::SigSpec s = sig.extract(big_endian ? sig.width - 1 - i : i, 1); - log_assert(s.chunks.size() == 1 && s.chunks[0].width == 1); + for (int i = 0; i < sig.__width; i++) { + RTLIL::SigSpec s = sig.extract(big_endian ? sig.__width - 1 - i : i, 1); + log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1); print_spice_net(f, s, neg, pos, ncpf, nc_counter); } } @@ -101,7 +101,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de } for (auto &conn : module->connections) - for (int i = 0; i < conn.first.width; i++) { + for (int i = 0; i < conn.first.__width; i++) { fprintf(f, "V%d", conn_counter++); print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter); print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter); -- cgit v1.2.3 From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- backends/spice/spice.cc | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index c7f832c64..8e894cafd 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -27,16 +27,16 @@ static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { - log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1); - if (s.__chunks[0].wire) { - if (s.__chunks[0].wire->width > 1) - fprintf(f, " %s[%d]", RTLIL::id2cstr(s.__chunks[0].wire->name), s.__chunks[0].offset); + log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); + if (s.chunks()[0].wire) { + if (s.chunks()[0].wire->width > 1) + fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks()[0].wire->name), s.chunks()[0].offset); else - fprintf(f, " %s", RTLIL::id2cstr(s.__chunks[0].wire->name)); + fprintf(f, " %s", RTLIL::id2cstr(s.chunks()[0].wire->name)); } else { - if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S0) + if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S0) fprintf(f, " %s", neg.c_str()); - else if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S1) + else if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S1) fprintf(f, " %s", pos.c_str()); else fprintf(f, " %s%d", ncpf.c_str(), nc_counter++); @@ -90,9 +90,9 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de } for (auto &sig : port_sigs) { - for (int i = 0; i < sig.__width; i++) { - RTLIL::SigSpec s = sig.extract(big_endian ? sig.__width - 1 - i : i, 1); - log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1); + for (int i = 0; i < sig.size(); i++) { + RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1); + log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); print_spice_net(f, s, neg, pos, ncpf, nc_counter); } } @@ -101,7 +101,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de } for (auto &conn : module->connections) - for (int i = 0; i < conn.first.__width; i++) { + for (int i = 0; i < conn.first.size(); i++) { fprintf(f, "V%d", conn_counter++); print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter); print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter); -- cgit v1.2.3 From 6aa792c864444324a1b140c2b63bd860f0cc3914 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 22:47:57 +0200 Subject: Replaced more old SigChunk programming patterns --- backends/spice/spice.cc | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 8e894cafd..e548df361 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -25,18 +25,17 @@ #include #include -static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) +static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { - log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); - if (s.chunks()[0].wire) { - if (s.chunks()[0].wire->width > 1) - fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks()[0].wire->name), s.chunks()[0].offset); + if (s.wire) { + if (s.wire->width > 1) + fprintf(f, " %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset); else - fprintf(f, " %s", RTLIL::id2cstr(s.chunks()[0].wire->name)); + fprintf(f, " %s", RTLIL::id2cstr(s.wire->name)); } else { - if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S0) + if (s == RTLIL::State::S0) fprintf(f, " %s", neg.c_str()); - else if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S1) + else if (s == RTLIL::State::S1) fprintf(f, " %s", pos.c_str()); else fprintf(f, " %s%d", ncpf.c_str(), nc_counter++); @@ -92,7 +91,6 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (auto &sig : port_sigs) { for (int i = 0; i < sig.size(); i++) { RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1); - log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); print_spice_net(f, s, neg, pos, ncpf, nc_counter); } } -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- backends/spice/spice.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index e548df361..a3784f115 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -58,7 +58,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de { log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name)); - for (auto &conn : cell->connections) { + for (auto &conn : cell->connections_) { RTLIL::SigSpec sig = sigmap(conn.second); port_sigs.push_back(sig); } @@ -80,8 +80,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - if (cell->connections.count(wire->name) > 0) { - sig = sigmap(cell->connections.at(wire->name)); + if (cell->connections_.count(wire->name) > 0) { + sig = sigmap(cell->connections_.at(wire->name)); sig.extend(wire->width, false); } port_sigs.push_back(sig); @@ -98,7 +98,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de fprintf(f, " %s\n", RTLIL::id2cstr(cell->type)); } - for (auto &conn : module->connections) + for (auto &conn : module->connections_) for (int i = 0; i < conn.first.size(); i++) { fprintf(f, "V%d", conn_counter++); print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter); -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- backends/spice/spice.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index a3784f115..4bc8710e9 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -58,7 +58,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de { log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name)); - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); port_sigs.push_back(sig); } @@ -80,8 +80,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - if (cell->connections_.count(wire->name) > 0) { - sig = sigmap(cell->connections_.at(wire->name)); + if (cell->connections().count(wire->name) > 0) { + sig = sigmap(cell->connections().at(wire->name)); sig.extend(wire->width, false); } port_sigs.push_back(sig); @@ -98,7 +98,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de fprintf(f, " %s\n", RTLIL::id2cstr(cell->type)); } - for (auto &conn : module->connections_) + for (auto &conn : module->connections()) for (int i = 0; i < conn.first.size(); i++) { fprintf(f, "V%d", conn_counter++); print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter); -- cgit v1.2.3 From 97a59851a6c411ccb06162d4b31725bf89262378 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 16:11:28 +0200 Subject: Added RTLIL::Cell::has(portname) --- backends/spice/spice.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 4bc8710e9..653a9f22d 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -80,7 +80,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - if (cell->connections().count(wire->name) > 0) { + if (cell->has(wire->name)) { sig = sigmap(cell->connections().at(wire->name)); sig.extend(wire->width, false); } -- cgit v1.2.3 From 3f4e3ca8ad480c2e73e2072ada77078ffd95e08f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 16:14:02 +0200 Subject: More RTLIL::Cell API usage cleanups --- backends/spice/spice.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 653a9f22d..077368771 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -81,7 +81,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); if (cell->has(wire->name)) { - sig = sigmap(cell->connections().at(wire->name)); + sig = sigmap(cell->get(wire->name)); sig.extend(wire->width, false); } port_sigs.push_back(sig); -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- backends/spice/spice.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 077368771..ef31e06a9 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -68,7 +68,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de RTLIL::Module *mod = design->modules.at(cell->type); std::vector ports; - for (auto wire_it : mod->wires) { + for (auto wire_it : mod->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) continue; @@ -195,7 +195,7 @@ struct SpiceBackend : public Backend { } std::vector ports; - for (auto wire_it : module->wires) { + for (auto wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) continue; -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- backends/spice/spice.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index ef31e06a9..c58e4bec5 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -47,7 +47,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de SigMap sigmap(module); int cell_counter = 0, conn_counter = 0, nc_counter = 0; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; fprintf(f, "X%d", cell_counter++); -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- backends/spice/spice.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index c58e4bec5..283448c3b 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -54,7 +54,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de std::vector port_sigs; - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) { log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name)); @@ -65,7 +65,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de } else { - RTLIL::Module *mod = design->modules.at(cell->type); + RTLIL::Module *mod = design->modules_.at(cell->type); std::vector ports; for (auto wire_it : mod->wires_) { @@ -171,14 +171,14 @@ struct SpiceBackend : public Backend { extra_args(f, filename, args, argidx); if (top_module_name.empty()) - for (auto & mod_it:design->modules) + for (auto & mod_it:design->modules_) if (mod_it.second->get_bool_attribute("\\top")) top_module_name = mod_it.first; fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str); fprintf(f, "\n"); - for (auto module_it : design->modules) + for (auto module_it : design->modules_) { RTLIL::Module *module = module_it.second; if (module->get_bool_attribute("\\blackbox")) -- cgit v1.2.3 From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- backends/spice/spice.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 283448c3b..ab5316ec3 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -23,7 +23,6 @@ #include "kernel/celltypes.h" #include "kernel/log.h" #include -#include static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { -- cgit v1.2.3 From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- backends/spice/spice.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index ab5316ec3..a445e9cc9 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -79,8 +79,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - if (cell->has(wire->name)) { - sig = sigmap(cell->get(wire->name)); + if (cell->hasPort(wire->name)) { + sig = sigmap(cell->getPort(wire->name)); sig.extend(wire->width, false); } port_sigs.push_back(sig); -- cgit v1.2.3 From 04727c7e0fb4c00b38999da192e4ada2a6f9474a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 18:58:40 +0200 Subject: No implicit conversion from IdString to anything else --- backends/spice/spice.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index a445e9cc9..be0086ffd 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -172,7 +172,7 @@ struct SpiceBackend : public Backend { if (top_module_name.empty()) for (auto & mod_it:design->modules_) if (mod_it.second->get_bool_attribute("\\top")) - top_module_name = mod_it.first; + top_module_name = mod_it.first.str(); fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str); fprintf(f, "\n"); -- cgit v1.2.3 From 5dce303a2a2c27d50e99856b6f33467798e13020 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 13:54:21 +0200 Subject: Changed backend-api from FILE to std::ostream --- backends/spice/spice.cc | 52 ++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index be0086ffd..b057063cd 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -24,24 +24,24 @@ #include "kernel/log.h" #include -static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) +static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { if (s.wire) { if (s.wire->width > 1) - fprintf(f, " %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset); + f << stringf(" %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset); else - fprintf(f, " %s", RTLIL::id2cstr(s.wire->name)); + f << stringf(" %s", RTLIL::id2cstr(s.wire->name)); } else { if (s == RTLIL::State::S0) - fprintf(f, " %s", neg.c_str()); + f << stringf(" %s", neg.c_str()); else if (s == RTLIL::State::S1) - fprintf(f, " %s", pos.c_str()); + f << stringf(" %s", pos.c_str()); else - fprintf(f, " %s%d", ncpf.c_str(), nc_counter++); + f << stringf(" %s%d", ncpf.c_str(), nc_counter++); } } -static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian) +static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian) { SigMap sigmap(module); int cell_counter = 0, conn_counter = 0, nc_counter = 0; @@ -49,7 +49,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - fprintf(f, "X%d", cell_counter++); + f << stringf("X%d", cell_counter++); std::vector port_sigs; @@ -94,15 +94,15 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de } } - fprintf(f, " %s\n", RTLIL::id2cstr(cell->type)); + f << stringf(" %s\n", RTLIL::id2cstr(cell->type)); } for (auto &conn : module->connections()) for (int i = 0; i < conn.first.size(); i++) { - fprintf(f, "V%d", conn_counter++); + f << stringf("V%d", conn_counter++); print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter); print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter); - fprintf(f, " DC 0\n"); + f << stringf(" DC 0\n"); } } @@ -133,7 +133,7 @@ struct SpiceBackend : public Backend { log(" set the specified module as design top module\n"); log("\n"); } - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) + virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) { std::string top_module_name; RTLIL::Module *top_module = NULL; @@ -174,8 +174,8 @@ struct SpiceBackend : public Backend { if (mod_it.second->get_bool_attribute("\\top")) top_module_name = mod_it.first.str(); - fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str); - fprintf(f, "\n"); + *f << stringf("* SPICE netlist generated by %s\n", yosys_version_str); + *f << stringf("\n"); for (auto module_it : design->modules_) { @@ -203,31 +203,31 @@ struct SpiceBackend : public Backend { ports.at(wire->port_id-1) = wire; } - fprintf(f, ".SUBCKT %s", RTLIL::id2cstr(module->name)); + *f << stringf(".SUBCKT %s", RTLIL::id2cstr(module->name)); for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); if (wire->width > 1) { for (int i = 0; i < wire->width; i++) - fprintf(f, " %s[%d]", RTLIL::id2cstr(wire->name), big_endian ? wire->width - 1 - i : i); + *f << stringf(" %s[%d]", RTLIL::id2cstr(wire->name), big_endian ? wire->width - 1 - i : i); } else - fprintf(f, " %s", RTLIL::id2cstr(wire->name)); + *f << stringf(" %s", RTLIL::id2cstr(wire->name)); } - fprintf(f, "\n"); - print_spice_module(f, module, design, neg, pos, ncpf, big_endian); - fprintf(f, ".ENDS %s\n\n", RTLIL::id2cstr(module->name)); + *f << stringf("\n"); + print_spice_module(*f, module, design, neg, pos, ncpf, big_endian); + *f << stringf(".ENDS %s\n\n", RTLIL::id2cstr(module->name)); } if (!top_module_name.empty()) { if (top_module == NULL) log_error("Can't find top module `%s'!\n", top_module_name.c_str()); - print_spice_module(f, top_module, design, neg, pos, ncpf, big_endian); - fprintf(f, "\n"); + print_spice_module(*f, top_module, design, neg, pos, ncpf, big_endian); + *f << stringf("\n"); } - fprintf(f, "************************\n"); - fprintf(f, "* end of SPICE netlist *\n"); - fprintf(f, "************************\n"); - fprintf(f, "\n"); + *f << stringf("************************\n"); + *f << stringf("* end of SPICE netlist *\n"); + *f << stringf("************************\n"); + *f << stringf("\n"); } } SpiceBackend; -- cgit v1.2.3