From d6c7aa0e3d9e64827a8305610bedcc9a9df88a49 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 11 Jan 2023 17:52:25 +0100 Subject: sim/formalff: Clock handling for yw cosim --- backends/smt2/smt2.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/smt2') diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 3b3585b59..1ab39a405 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -998,7 +998,7 @@ struct Smt2Worker if (contains_clock && GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig))) comments.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire), clock_posedge.count(sig) ? " posedge" : "", clock_negedge.count(sig) ? " negedge" : "")); - if (contains_clock) { + if (wire->port_input && contains_clock) { for (int i = 0; i < GetSize(sig); i++) { bool is_posedge = clock_posedge.count(sig[i]); bool is_negedge = clock_negedge.count(sig[i]); -- cgit v1.2.3