From 9419de3e371451f7f0eb51e89cab3fa8bebba26c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Dec 2017 03:05:20 +0100 Subject: Add yosys-smtbmc VCD writer support for memories with async writes --- backends/smt2/smtbmc.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'backends/smt2/smtbmc.py') diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index 560e39d86..c86b520a2 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -594,7 +594,7 @@ def write_vcd_trace(steps_start, steps_stop, index): mem_trace_data = dict() for mempath in sorted(smt.hiermems(topmod)): - abits, width, rports, wports = smt.mem_info(topmod, mempath) + abits, width, rports, wports, asyncwr = smt.mem_info(topmod, mempath) expr_id = list() expr_list = list() @@ -666,7 +666,8 @@ def write_vcd_trace(steps_start, steps_stop, index): else: buf[k] = tdata[i][k] - tdata.append(data[:]) + if not asyncwr: + tdata.append(data[:]) for j_data in wdata[i]: if j_data["A"] != addr: @@ -679,6 +680,9 @@ def write_vcd_trace(steps_start, steps_stop, index): if M[k] == "1": data[k] = D[k] + if asyncwr: + tdata.append(data[:]) + assert len(tdata) == len(rdata) netpath = mempath[:] @@ -785,7 +789,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): mems = sorted(smt.hiermems(vlogtb_topmod)) for mempath in mems: - abits, width, rports, wports = smt.mem_info(vlogtb_topmod, mempath) + abits, width, rports, wports, asyncwr = smt.mem_info(vlogtb_topmod, mempath) addr_expr_list = list() data_expr_list = list() @@ -888,7 +892,7 @@ def write_constr_trace(steps_start, steps_stop, index): mems = sorted(smt.hiermems(constr_topmod)) for mempath in mems: - abits, width, rports, wports = smt.mem_info(constr_topmod, mempath) + abits, width, rports, wports, asyncwr = smt.mem_info(constr_topmod, mempath) addr_expr_list = list() data_expr_list = list() -- cgit v1.2.3