From 5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c Mon Sep 17 00:00:00 2001 From: Vamsi K Vytla Date: Mon, 27 Apr 2020 09:44:24 -0700 Subject: Preserve 'signed'-ness of a verilog wire through RTLIL As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser --- backends/json/json.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'backends/json/json.cc') diff --git a/backends/json/json.cc b/backends/json/json.cc index 1a8b757ef..5edc50f60 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -160,6 +160,8 @@ struct JsonWriter f << stringf(" \"offset\": %d,\n", w->start_offset); if (w->upto) f << stringf(" \"upto\": 1,\n"); + if (w->is_signed) + f << stringf(" \"signed\": %d,\n", w->is_signed); f << stringf(" \"bits\": %s\n", get_bits(w).c_str()); f << stringf(" }"); first = false; @@ -227,6 +229,8 @@ struct JsonWriter f << stringf(" \"offset\": %d,\n", w->start_offset); if (w->upto) f << stringf(" \"upto\": 1,\n"); + if (w->is_signed) + f << stringf(" \"signed\": %d,\n", w->is_signed); f << stringf(" \"attributes\": {"); write_parameters(w->attributes); f << stringf("\n }\n"); -- cgit v1.2.3