From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- backends/intersynth/intersynth.cc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 47c1125f7..049a2ce84 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -30,23 +30,23 @@ static std::string netname(std::set &conntypes_code, std::setwidth) + if (sig.__chunks[0].offset != 0 || sig.__width != sig.__chunks[0].wire->width) goto error; - return RTLIL::unescape_id(sig.chunks[0].wire->name); + return RTLIL::unescape_id(sig.__chunks[0].wire->name); } struct IntersynthBackend : public Backend { @@ -177,9 +177,9 @@ struct IntersynthBackend : public Backend { node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); for (auto &port : cell->connections) { RTLIL::SigSpec sig = sigmap(port.second); - if (sig.width != 0) { - conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width)); - celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); + if (sig.__width != 0) { + conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.__width, sig.__width, sig.__width)); + celltype_code += stringf(" b%d %s%s", sig.__width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); } } -- cgit v1.2.3 From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- backends/intersynth/intersynth.cc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 049a2ce84..832922def 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -30,23 +30,23 @@ static std::string netname(std::set &conntypes_code, std::setwidth) + if (sig.chunks()[0].offset != 0 || sig.size() != sig.chunks()[0].wire->width) goto error; - return RTLIL::unescape_id(sig.__chunks[0].wire->name); + return RTLIL::unescape_id(sig.chunks()[0].wire->name); } struct IntersynthBackend : public Backend { @@ -177,9 +177,9 @@ struct IntersynthBackend : public Backend { node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); for (auto &port : cell->connections) { RTLIL::SigSpec sig = sigmap(port.second); - if (sig.__width != 0) { - conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.__width, sig.__width, sig.__width)); - celltype_code += stringf(" b%d %s%s", sig.__width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); + if (sig.size() != 0) { + conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); + celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); } } -- cgit v1.2.3 From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:32:28 +0200 Subject: Removed RTLIL::SigSpec::optimize() --- backends/intersynth/intersynth.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 832922def..a4cad5add 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -28,8 +28,6 @@ static std::string netname(std::set &conntypes_code, std::set &celltypes_code, std::set &constcells_code, RTLIL::SigSpec sig) { - sig.optimize(); - if (sig.chunks().size() != 1) error: log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig)); -- cgit v1.2.3 From 6aa792c864444324a1b140c2b63bd860f0cc3914 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 22:47:57 +0200 Subject: Replaced more old SigChunk programming patterns --- backends/intersynth/intersynth.cc | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index a4cad5add..b2e472bf3 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -28,23 +28,19 @@ static std::string netname(std::set &conntypes_code, std::set &celltypes_code, std::set &constcells_code, RTLIL::SigSpec sig) { - if (sig.chunks().size() != 1) -error: + if (!sig.is_fully_const() && !sig.is_wire()) log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig)); conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); - if (sig.chunks()[0].wire == NULL) { + if (sig.is_fully_const()) { celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.size(), sig.size(), sig.size())); - constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.size(), sig.chunks()[0].data.as_int(), - sig.size(), sig.size(), sig.chunks()[0].data.as_int(), sig.chunks()[0].data.as_int())); - return stringf("CONST_%d_0x%x", sig.size(), sig.chunks()[0].data.as_int()); + constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", + sig.size(), sig.as_int(), sig.size(), sig.size(), sig.as_int(), sig.as_int())); + return stringf("CONST_%d_0x%x", sig.size(), sig.as_int()); } - if (sig.chunks()[0].offset != 0 || sig.size() != sig.chunks()[0].wire->width) - goto error; - - return RTLIL::unescape_id(sig.chunks()[0].wire->name); + return RTLIL::unescape_id(sig.as_wire()->name); } struct IntersynthBackend : public Backend { -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- backends/intersynth/intersynth.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index b2e472bf3..8231f1d81 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -169,7 +169,7 @@ struct IntersynthBackend : public Backend { celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type)); node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - for (auto &port : cell->connections) { + for (auto &port : cell->connections_) { RTLIL::SigSpec sig = sigmap(port.second); if (sig.size() != 0) { conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- backends/intersynth/intersynth.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 8231f1d81..8c08747c3 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -169,7 +169,7 @@ struct IntersynthBackend : public Backend { celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type)); node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - for (auto &port : cell->connections_) { + for (auto &port : cell->connections()) { RTLIL::SigSpec sig = sigmap(port.second); if (sig.size() != 0) { conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- backends/intersynth/intersynth.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 8c08747c3..4e8c321bb 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -147,7 +147,7 @@ struct IntersynthBackend : public Backend { netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name)); // Module Ports: "std::set celltypes_code" prevents duplicate top level ports - for (auto wire_it : module->wires) { + for (auto wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_input || wire->port_output) { celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n", -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- backends/intersynth/intersynth.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 4e8c321bb..a463f5ece 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -128,7 +128,7 @@ struct IntersynthBackend : public Backend { if (module->get_bool_attribute("\\blackbox")) continue; - if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0) + if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0) continue; if (selected && !design->selected_whole_module(module->name)) { @@ -159,7 +159,7 @@ struct IntersynthBackend : public Backend { } // Submodules: "std::set celltypes_code" prevents duplicate cell types - for (auto cell_it : module->cells) + for (auto cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; std::string celltype_code, node_code; -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- backends/intersynth/intersynth.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index a463f5ece..2f94e290d 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -121,7 +121,7 @@ struct IntersynthBackend : public Backend { for (auto lib : libs) ct.setup_design(lib); - for (auto module_it : design->modules) + for (auto module_it : design->modules_) { RTLIL::Module *module = module_it.second; SigMap sigmap(module); -- cgit v1.2.3 From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- backends/intersynth/intersynth.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 2f94e290d..9faed77c9 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -23,7 +23,6 @@ #include "kernel/celltypes.h" #include "kernel/log.h" #include -#include static std::string netname(std::set &conntypes_code, std::set &celltypes_code, std::set &constcells_code, RTLIL::SigSpec sig) -- cgit v1.2.3 From 5dce303a2a2c27d50e99856b6f33467798e13020 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 13:54:21 +0200 Subject: Changed backend-api from FILE to std::ostream --- backends/intersynth/intersynth.cc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 9faed77c9..97ead3c64 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -69,7 +69,7 @@ struct IntersynthBackend : public Backend { log("http://www.clifford.at/intersynth/\n"); log("\n"); } - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) + virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) { log_header("Executing INTERSYNTH backend.\n"); log_push(); @@ -198,15 +198,15 @@ struct IntersynthBackend : public Backend { } if (!flag_notypes) { - fprintf(f, "### Connection Types\n"); + *f << stringf("### Connection Types\n"); for (auto code : conntypes_code) - fprintf(f, "%s", code.c_str()); - fprintf(f, "\n### Cell Types\n"); + *f << stringf("%s", code.c_str()); + *f << stringf("\n### Cell Types\n"); for (auto code : celltypes_code) - fprintf(f, "%s", code.c_str()); + *f << stringf("%s", code.c_str()); } - fprintf(f, "\n### Netlists\n"); - fprintf(f, "%s", netlists_code.c_str()); + *f << stringf("\n### Netlists\n"); + *f << stringf("%s", netlists_code.c_str()); for (auto lib : libs) delete lib; -- cgit v1.2.3 From 19cff41eb4261b20374058f16807a229af46f304 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 15:03:55 +0200 Subject: Changed frontend-api from FILE to std::istream --- backends/intersynth/intersynth.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backends/intersynth') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 97ead3c64..8502d90fc 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -101,13 +101,13 @@ struct IntersynthBackend : public Backend { log("Output filename: %s\n", filename.c_str()); for (auto filename : libfiles) { - FILE *f = fopen(filename.c_str(), "rt"); - if (f == NULL) + std::ifstream f; + f.open(filename.c_str()); + if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); libs.push_back(lib); - fclose(f); } if (libs.size() > 0) -- cgit v1.2.3