From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- backends/blif/blif.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/blif') diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index cb40834b3..7ae9965d5 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -103,7 +103,7 @@ struct BlifDumper std::map inputs, outputs; - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_input) inputs[wire->port_id] = wire; -- cgit v1.2.3