From 2d9484c12cd1fd96eca5253c876ad545ed209f40 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 15:40:28 -0700 Subject: When two boxes connect to each other, need not be a (* keep *) --- backends/aiger/xaiger.cc | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index fa6ba0aca..cbce4c83b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -405,12 +405,7 @@ struct XAigerWriter if (O != b) alias_map[O] = b; undriven_bits.erase(O); - - auto jt = input_bits.find(b); - if (jt != input_bits.end()) { - log_assert(keep_bits.count(O)); - input_bits.erase(b); - } + input_bits.erase(b); } } } -- cgit v1.2.3 From c340fbfab23c582103402bbd812d9bca4510dc41 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 21:58:04 -0700 Subject: Force $inout.out ports to begin with '$' to indicate internal --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cbce4c83b..21b281708 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -424,7 +424,7 @@ struct XAigerWriter // inherit existing inout's drivers if ((wire->port_input && wire->port_output && !undriven_bits.count(bit)) || keep_bits.count(bit)) { - RTLIL::IdString wire_name = wire->name.str() + "$inout.out"; + RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str()); RTLIL::Wire *new_wire = module->wire(wire_name); if (!new_wire) new_wire = module->addWire(wire_name, GetSize(wire)); -- cgit v1.2.3 From 44374b1b2b0dbc455c9e43d713e133d7d78a5e1a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 21:58:40 -0700 Subject: "abc_padding" attr for blackbox outputs that were padded, remove them later --- backends/aiger/xaiger.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 21b281708..5e49f3c80 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -350,6 +350,8 @@ struct XAigerWriter if (!box_module || !box_module->attributes.count("\\abc_box_id")) continue; + bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); + // Fully pad all unused input connections of this box cell with S0 // Fully pad all undriven output connections of this box cell with anonymous wires // NB: Assume box_module->ports are sorted alphabetically @@ -394,7 +396,10 @@ struct XAigerWriter rhs = it->second; } else { - rhs = module->addWire(NEW_ID, GetSize(w)); + Wire *wire = module->addWire(NEW_ID, GetSize(w)); + if (blackbox) + wire->set_bool_attribute(ID(abc_padding)); + rhs = wire; cell->setPort(port_name, rhs); } -- cgit v1.2.3 From d0493925ec739aa13cd72e5aa525e98ca49cc326 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 28 Sep 2019 09:28:51 +0200 Subject: Support binary files for backends, fixes #1407 --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index fa6ba0aca..87ba0aedf 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -856,7 +856,7 @@ struct XAigerBackend : public Backend { } break; } - extra_args(f, filename, args, argidx); + extra_args(f, filename, args, argidx, !ascii_mode); Module *top_module = design->top_module(); -- cgit v1.2.3 From 0c380f085576c2cead5e3576825cb60046bfd76b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 28 Sep 2019 09:50:29 +0200 Subject: Add aiger and protobuf backends binary support --- backends/aiger/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/aiger') diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 0798fb35d..3e8b14dee 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -777,7 +777,7 @@ struct AigerBackend : public Backend { } break; } - extra_args(f, filename, args, argidx); + extra_args(f, filename, args, argidx, !ascii_mode); Module *top_module = design->top_module(); -- cgit v1.2.3 From aae2b9fd9c8dc915fadacc24962436dd7aedff36 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 11:04:10 -0700 Subject: Rename abc_* names/attributes to more precisely be abc9_* --- backends/aiger/xaiger.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 4018cc9de..46890b071 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -203,7 +203,7 @@ struct XAigerWriter // box ordering, but not individual AIG cells dict> bit_drivers, bit_users; TopoSort toposort; - bool abc_box_seen = false; + bool abc9_box_seen = false; for (auto cell : module->selected_cells()) { if (cell->type == "$_NOT_") @@ -242,8 +242,8 @@ struct XAigerWriter log_assert(!holes_mode); RTLIL::Module* inst_module = module->design->module(cell->type); - if (inst_module && inst_module->attributes.count("\\abc_box_id")) { - abc_box_seen = true; + if (inst_module && inst_module->attributes.count("\\abc9_box_id")) { + abc9_box_seen = true; if (!holes_mode) { toposort.node(cell->name); @@ -291,10 +291,10 @@ struct XAigerWriter if (is_output) { int arrival = 0; if (port_wire) { - auto it = port_wire->attributes.find("\\abc_arrival"); + auto it = port_wire->attributes.find("\\abc9_arrival"); if (it != port_wire->attributes.end()) { if (it->second.flags != 0) - log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type)); + log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type)); arrival = it->second.as_int(); } } @@ -318,7 +318,7 @@ struct XAigerWriter //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); } - if (abc_box_seen) { + if (abc9_box_seen) { for (auto &it : bit_users) if (bit_drivers.count(it.first)) for (auto driver_cell : bit_drivers.at(it.first)) @@ -347,7 +347,7 @@ struct XAigerWriter log_assert(cell); RTLIL::Module* box_module = module->design->module(cell->type); - if (!box_module || !box_module->attributes.count("\\abc_box_id")) + if (!box_module || !box_module->attributes.count("\\abc9_box_id")) continue; bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); @@ -398,7 +398,7 @@ struct XAigerWriter else { Wire *wire = module->addWire(NEW_ID, GetSize(w)); if (blackbox) - wire->set_bool_attribute(ID(abc_padding)); + wire->set_bool_attribute(ID(abc9_padding)); rhs = wire; cell->setPort(port_name, rhs); } @@ -666,7 +666,7 @@ struct XAigerWriter write_h_buffer(box_inputs); write_h_buffer(box_outputs); - write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int()); + write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int()); write_h_buffer(box_count++); } -- cgit v1.2.3 From 5110a34dd74bc96c47d4aef47bc155110de2d87e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 4 Nov 2019 14:25:13 +0100 Subject: Fix write_aiger bug added in 524af21 Signed-off-by: Clifford Wolf --- backends/aiger/aiger.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'backends/aiger') diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 3e8b14dee..44718baae 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -91,6 +91,9 @@ struct AigerWriter } else if (alias_map.count(bit)) { a = bit2aig(alias_map.at(bit)); + } else + if (initstate_bits.count(bit)) { + a = initstate_ff; } if (bit == State::Sx || bit == State::Sz) -- cgit v1.2.3