From 5017be6445fdf3729eb8781e1692be1099039a90 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Dec 2019 14:49:09 -0800 Subject: Cope with abc9_arrival as string --- backends/aiger/xaiger.cc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 5729f045a..96263f576 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -199,6 +199,7 @@ struct XAigerWriter dict> bit_drivers, bit_users; TopoSort toposort; bool abc9_box_seen = false; + std::vector arrivals; for (auto cell : module->selected_cells()) { if (cell->type == "$_NOT_") @@ -284,16 +285,20 @@ struct XAigerWriter } } if (is_output) { - int arrival = 0; + arrivals.clear(); if (port_wire) { auto it = port_wire->attributes.find("\\abc9_arrival"); if (it != port_wire->attributes.end()) { - if (it->second.flags != 0) - log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type)); - arrival = it->second.as_int(); + if (it->second.flags == 0) + arrivals.push_back(it->second.as_int()); + else + for (const auto &tok : split_tokens(it->second.decode_string())) + arrivals.push_back(atoi(tok.c_str())); } } + log_assert(GetSize(arrivals) <= 1 || GetSize(arrivals) == GetSize(c.second)); + auto it = arrivals.begin(); for (auto b : c.second) { Wire *w = b.wire; if (!w) continue; @@ -303,8 +308,12 @@ struct XAigerWriter alias_map[O] = b; undriven_bits.erase(O); - if (arrival) - arrival_times[b] = arrival; + if (!arrivals.empty()) { + if (arrivals.size() == 1) + arrival_times[b] = *it; + else + arrival_times[b] = *it++; + } } } } -- cgit v1.2.3 From 36d79c80d05f93cd4cb565fe7a92d7cb88683852 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Dec 2019 15:35:19 -0800 Subject: write_xaiger: simplify c{i,o}_bits --- backends/aiger/xaiger.cc | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 96263f576..db38f2017 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -81,8 +81,7 @@ struct XAigerWriter pool input_bits, output_bits; dict not_map, alias_map; dict> and_map; - vector> ci_bits; - vector> co_bits; + vector ci_bits, co_bits; dict arrival_times; vector> aig_gates; @@ -376,7 +375,6 @@ struct XAigerWriter cell->setPort(port_name, rhs); } - int offset = 0; for (auto b : rhs.bits()) { SigBit I = sigmap(b); if (b == RTLIL::Sx) @@ -387,7 +385,7 @@ struct XAigerWriter else alias_map[b] = I; } - co_bits.emplace_back(b, cell, port_name, offset++, 0); + co_bits.emplace_back(b); unused_bits.erase(b); } } @@ -407,9 +405,8 @@ struct XAigerWriter cell->setPort(port_name, rhs); } - int offset = 0; for (const auto &b : rhs.bits()) { - ci_bits.emplace_back(b, cell, port_name, offset++); + ci_bits.emplace_back(b); SigBit O = sigmap(b); if (O != b) alias_map[O] = b; @@ -496,15 +493,13 @@ struct XAigerWriter aig_map[bit] = 2*aig_m; } - for (auto &c : ci_bits) { - RTLIL::SigBit bit = std::get<0>(c); + for (auto bit : ci_bits) { aig_m++, aig_i++; aig_map[bit] = 2*aig_m; } - for (auto &c : co_bits) { - RTLIL::SigBit bit = std::get<0>(c); - std::get<4>(c) = ordered_outputs[bit] = aig_o++; + for (auto bit : co_bits) { + ordered_outputs[bit] = aig_o++; aig_outputs.push_back(bit2aig(bit)); } @@ -517,7 +512,6 @@ struct XAigerWriter ordered_outputs[bit] = aig_o++; aig_outputs.push_back(bit2aig(bit)); } - } void write_aiger(std::ostream &f, bool ascii_mode) -- cgit v1.2.3 From 3177437224b1264e429df34683c3369227657446 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 9 Jan 2020 10:05:03 -0800 Subject: write_xaiger: cope with abc9_arrival as string of ints --- backends/aiger/xaiger.cc | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index beaed696d..1956422bc 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -185,6 +185,7 @@ struct XAigerWriter } } + std::vector arrivals; for (auto cell : module->cells()) { if (cell->type == "$_NOT_") { @@ -224,13 +225,15 @@ struct XAigerWriter } RTLIL::Module* inst_module = module->design->module(cell->type); - if (inst_module) { + if (inst_module && inst_module->get_blackbox_attribute()) { auto it = cell->attributes.find("\\abc9_box_seq"); if (it != cell->attributes.end()) { int abc9_box_seq = it->second.as_int(); if (GetSize(box_list) <= abc9_box_seq) box_list.resize(abc9_box_seq+1); box_list[abc9_box_seq] = cell; + // Only flop boxes may have arrival times + // (all others are combinatorial) if (!inst_module->get_bool_attribute("\\abc9_flop")) continue; } @@ -238,16 +241,26 @@ struct XAigerWriter for (const auto &conn : cell->connections()) { auto port_wire = inst_module->wire(conn.first); if (port_wire->port_output) { - int arrival = 0; + arrivals.clear(); auto it = port_wire->attributes.find("\\abc9_arrival"); if (it != port_wire->attributes.end()) { - if (it->second.flags != 0) - log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type)); - arrival = it->second.as_int(); + if (it->second.flags == 0) + arrivals.emplace_back(it->second.as_int()); + else + for (const auto &tok : split_tokens(it->second.decode_string())) + arrivals.push_back(atoi(tok.c_str())); + } + if (!arrivals.empty()) { + if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) + log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), + GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); + auto jt = arrivals.begin(); + for (auto bit : sigmap(conn.second)) { + arrival_times[bit] = *jt; + if (arrivals.size() > 1) + jt++; + } } - if (arrival) - for (auto bit : sigmap(conn.second)) - arrival_times[bit] = arrival; } } } -- cgit v1.2.3 From ceabd5bc3984a0ff088d697ac8ba7061b4f552fb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 9 Jan 2020 14:03:43 -0800 Subject: write_xaiger: cleanup --- backends/aiger/xaiger.cc | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 1956422bc..cde53ff63 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -243,23 +243,21 @@ struct XAigerWriter if (port_wire->port_output) { arrivals.clear(); auto it = port_wire->attributes.find("\\abc9_arrival"); - if (it != port_wire->attributes.end()) { - if (it->second.flags == 0) - arrivals.emplace_back(it->second.as_int()); - else - for (const auto &tok : split_tokens(it->second.decode_string())) - arrivals.push_back(atoi(tok.c_str())); - } - if (!arrivals.empty()) { - if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) - log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), - GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); - auto jt = arrivals.begin(); - for (auto bit : sigmap(conn.second)) { - arrival_times[bit] = *jt; - if (arrivals.size() > 1) - jt++; - } + if (it == port_wire->attributes.end()) + continue; + if (it->second.flags == 0) + arrivals.emplace_back(it->second.as_int()); + else + for (const auto &tok : split_tokens(it->second.decode_string())) + arrivals.push_back(atoi(tok.c_str())); + if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) + log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), + GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); + auto jt = arrivals.begin(); + for (auto bit : sigmap(conn.second)) { + arrival_times[bit] = *jt; + if (arrivals.size() > 1) + jt++; } } } -- cgit v1.2.3 From f24de88f385a3eeaadd9b9c8c200a7c338f37448 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 10 Jan 2020 17:13:27 -0800 Subject: log_debug() for abc9_{arrival,required} times --- backends/aiger/xaiger.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cde53ff63..359d951b9 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -254,6 +254,14 @@ struct XAigerWriter log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); auto jt = arrivals.begin(); + +#ifndef NDEBUG + if (ys_debug(1)) { + static std::set> seen; + if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); + } +#endif + for (auto bit : sigmap(conn.second)) { arrival_times[bit] = *jt; if (arrivals.size() > 1) -- cgit v1.2.3 From aaafd784a54603af44fe7424c8d39be2443368e5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Jan 2020 13:05:39 -0800 Subject: write_xaiger: skip if no arrival times --- backends/aiger/xaiger.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index d3415e45d..b424eca2c 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -257,6 +257,9 @@ struct XAigerWriter arrivals.push_back(atoi(tok.c_str())); } + if (arrivals.empty()) + continue; + if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); -- cgit v1.2.3 From 0e4285ca0d92397490768e649626cfdb5a0c9d95 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Jan 2020 15:05:49 -0800 Subject: abc9_ops: generate flop box ids, add abc9_required to FD* cells --- backends/aiger/xaiger.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 20f2385f6..268be432a 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -596,7 +596,11 @@ struct XAigerWriter RTLIL::Module* box_module = module->design->module(cell->type); log_assert(box_module); - auto r = cell_cache.insert(cell->type); + IdString derived_type = box_module->derive(box_module->design, cell->parameters); + box_module = box_module->design->module(derived_type); + log_assert(box_module); + + auto r = cell_cache.insert(derived_type); auto &v = r.first->second; if (r.second) { int box_inputs = 0, box_outputs = 0; -- cgit v1.2.3 From 485e08e4363f2aa93204f8bcc6c1ff5243936ea6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Jan 2020 16:33:41 -0800 Subject: abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *) --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/aiger') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index c2d076c86..66ddbde33 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -318,7 +318,7 @@ struct XAigerWriter RTLIL::Module* box_module = module->design->module(cell->type); log_assert(box_module); - log_assert(box_module->attributes.count("\\abc9_box_id")); + log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop")); auto r = box_ports.insert(cell->type); if (r.second) { -- cgit v1.2.3