From 227520f94d5fe0eb983889b61ed9b72640f1b4f4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 25 Mar 2013 17:13:14 +0100 Subject: Added nosync attribute and some async reset related fixes --- README | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'README') diff --git a/README b/README index e86d92d4f..ab9fcd612 100644 --- a/README +++ b/README @@ -199,6 +199,12 @@ Verilog Attributes and non-standard features prohibits the generation of logic-loops for latches. Instead all not explicitly assigned values default to x-bits. +- The "nosync" attribute on registers prohibits the generation of a + storage element. The register itself will always have all bits set + to 'x' (undefined). The variable may only be used as blocking assigned + temporary variable within an always block. This is mostly used internally + by yosys to synthesize verilog functions and access arrays. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset -- cgit v1.2.3