From 0b8cfbc6fde8e7500c5df38c74e1da2d74e588bd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 29 Sep 2014 12:51:54 +0200 Subject: Added support for "keep" on modules --- README | 2 ++ 1 file changed, 2 insertions(+) (limited to 'README') diff --git a/README b/README index d7f5aaa4b..32a47cbfe 100644 --- a/README +++ b/README @@ -273,6 +273,8 @@ Verilog Attributes and non-standard features - The "keep" attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that have hidden connections that are not part of the netlist, such as IO pads. + Setting the "keep" attribute on a module has the same effect as setting it + on all instances of the module. - The "init" attribute on wires is set by the frontend when a register is initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis -- cgit v1.2.3