From 0488492ad269df9641ab317eac5568353dd61076 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 22 Nov 2019 15:32:46 +0000
Subject: Update CHANGELOG and README

Signed-off-by: David Shah <dave@ds0.me>
---
 README.md | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'README.md')

diff --git a/README.md b/README.md
index 77e9410da..327d407f9 100644
--- a/README.md
+++ b/README.md
@@ -387,6 +387,10 @@ Verilog Attributes and non-standard features
   according to the type of the always. These are checked for correctness in
   ``proc_dlatch``.
 
+- The cell attribute ``wildcard_port_conns`` represents wildcard port
+  connections (SystemVerilog ``.*``). These are resolved to concrete
+  connections to matching wires in ``hierarchy``.  
+
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset
-- 
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