From 577545488a81e1f9b84b214d6d02187aac28af6c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Feb 2020 14:22:43 -0800 Subject: xilinx: use specify blocks in place of abc9_{arrival,required} --- README.md | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 9c15fe3d9..8cd347497 100644 --- a/README.md +++ b/README.md @@ -364,25 +364,14 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. -- The module attribute ``abc9_box_id`` specifies a positive integer linking a - blackbox or whitebox definition to a corresponding entry in a `abc9` - box-file. +- The module attribute ``abc9_box`` is a boolean specifying a blackbox or + whitebox definition for use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. -- The output port attribute ``abc9_arrival`` specifies an integer, or a string - of space-separated integers to be used as the arrival time of this blackbox - port. It can be used, for example, to specify the clk-to-Q delay of a flip- - flop output for consideration during `abc9` techmapping. - -- The input port attribute ``abc9_required`` specifies an integer, or a string - of space-separated integers to be used as the required time of this blackbox - port. It can be used, for example, to specify the setup-time of a flip-flop - input for consideration during `abc9` techmapping. - - The module attribute ``abc9_flop`` is a boolean marking the module as a flip-flop. This allows `abc9` to analyse its contents in order to perform sequential synthesis. -- cgit v1.2.3 From 12d70ca8fbad73f2615e711e786f8b90fa005bee Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Feb 2020 15:25:30 -0800 Subject: xilinx: improve specify functionality --- README.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 8cd347497..08d4cb0d7 100644 --- a/README.md +++ b/README.md @@ -364,8 +364,13 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. +- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9` + that this module describes a LUT with propagation delays described using + `specify` statements. + - The module attribute ``abc9_box`` is a boolean specifying a blackbox or - whitebox definition for use by `abc9`. + whitebox definition, with propagation delays described using `specify` + statements, for use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for -- cgit v1.2.3 From 0f4c1906bb82f03f77683b71e597ed4802fe316a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 27 Feb 2020 10:29:53 -0800 Subject: Small fixes --- README.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 08d4cb0d7..79801d23f 100644 --- a/README.md +++ b/README.md @@ -364,13 +364,13 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. -- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9` - that this module describes a LUT with propagation delays described using - `specify` statements. +- The module attribute ``abc9_lut`` is an integer attribute indicating to + `abc9` that this module describes a LUT with an area cost of this value, and + propagation delays described using `specify` statements. -- The module attribute ``abc9_box`` is a boolean specifying a blackbox or - whitebox definition, with propagation delays described using `specify` - statements, for use by `abc9`. +- The module attribute ``abc9_box`` is a boolean specifying a black/white-box + definition, with propagation delays described using `specify` statements, for + use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for -- cgit v1.2.3