From 27377c46634263beb5f8c28cb34b0c87ed6e9525 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 23 Sep 2019 12:12:02 +0300 Subject: Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. --- Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'Makefile') diff --git a/Makefile b/Makefile index 2cac80f0f..742692f0d 100644 --- a/Makefile +++ b/Makefile @@ -710,6 +710,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/anlogic && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" -- cgit v1.2.3