From 4569a747f8af3880e23408eb93323afc8088b78b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 10 Oct 2014 16:59:44 +0200 Subject: Renamed SIZE() to GetSize() because of name collision on Win32 --- CodingReadme | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 8f515e1f4..2404a7a5a 100644 --- a/CodingReadme +++ b/CodingReadme @@ -61,8 +61,8 @@ Yosys is written in C++11. At the moment only constructs supported by gcc 4.6 is allowed in Yosys code. This will change in future releases. In general Yosys uses "int" instead of "size_t". To avoid compiler -warnings for implicit type casts, always use "SIZE(foobar)" instead -of "foobar.size()". (the macro SIZE() is defined by kernel/yosys.h) +warnings for implicit type casts, always use "GetSize(foobar)" instead +of "foobar.size()". (GetSize() is defined by kernel/yosys.h) Use range-based for loops whenever applicable. -- cgit v1.2.3 From c321b419d45be8c25bac671df776a779da78b090 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 17 Oct 2014 16:39:24 +0200 Subject: Added notes regarding building in VS --- CodingReadme | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 2404a7a5a..8bcbe6125 100644 --- a/CodingReadme +++ b/CodingReadme @@ -67,6 +67,41 @@ of "foobar.size()". (GetSize() is defined by kernel/yosys.h) Use range-based for loops whenever applicable. +Building in Visual Studio +========================= + +1. Create an empty Visual C++ Win32 Console App project + (recommended name: YosysVS) + +2. Close VS and launch "Git Bash" in the project directory + +3. Prepare sources + + git clone https://github.com/cliffordwolf/yosys.git yosys + cd yosys + + curl -O http://www.clifford.at/yosys/nogit/yosys-win32-.zip + unzip yosys-win32-.zip + unzip yosys-win32-/genfiles.zip + +4. Add files to VS project + + notepad vcxproj_files.txt + notepad ../YosysVS/YosysVS.vcxproj + + (replace the empty in YosysVS.vcxproj + with the XML text from vcxproj_files.txt) + +5. Open project in VS and go to the project properties: + + C/C++ -> General -> Additional Include Directories + Add: ..\yosys + + C/C++ -> Preprocessor -> Preprocessor Definitions + Add: _YOSYS_;_CRT_SECURE_NO_WARNINGS + +6. Build YosysVS + Checklist for adding internal cell types ======================================== -- cgit v1.2.3 From 85572b05e5359f28c1625b873dc14428f796a454 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 18 Oct 2014 15:17:33 +0200 Subject: Create vcxsrc in mxe build "make dist" --- CodingReadme | 46 ++++++++++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 20 deletions(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 8bcbe6125..0e3ff6949 100644 --- a/CodingReadme +++ b/CodingReadme @@ -67,32 +67,27 @@ of "foobar.size()". (GetSize() is defined by kernel/yosys.h) Use range-based for loops whenever applicable. -Building in Visual Studio -========================= -1. Create an empty Visual C++ Win32 Console App project - (recommended name: YosysVS) - -2. Close VS and launch "Git Bash" in the project directory +Creating the Visual Studio Template Project +=========================================== -3. Prepare sources - - git clone https://github.com/cliffordwolf/yosys.git yosys - cd yosys +1. Create an empty Visual C++ Win32 Console App project - curl -O http://www.clifford.at/yosys/nogit/yosys-win32-.zip - unzip yosys-win32-.zip - unzip yosys-win32-/genfiles.zip + Microsoft Visual Studio Express 2013 for Windows Desktop + Open New Project Wizard (File -> New Project..) -4. Add files to VS project + Project Name: YosysVS + Solution Name: YosysVS + [X] Create directory for solution + [ ] Add to source control - notepad vcxproj_files.txt - notepad ../YosysVS/YosysVS.vcxproj + [X] Console applications + [X] Empty Projcect + [ ] SDL checks - (replace the empty in YosysVS.vcxproj - with the XML text from vcxproj_files.txt) +2. Open YosysVS Project Properties -5. Open project in VS and go to the project properties: + Select Configuration: All Configurations C/C++ -> General -> Additional Include Directories Add: ..\yosys @@ -100,7 +95,18 @@ Building in Visual Studio C/C++ -> Preprocessor -> Preprocessor Definitions Add: _YOSYS_;_CRT_SECURE_NO_WARNINGS -6. Build YosysVS +3. Resulting file system tree: + + YosysVS/ + YosysVS/YosysVS + YosysVS/YosysVS/YosysVS.vcxproj + YosysVS/YosysVS/YosysVS.vcxproj.filters + YosysVS/YosysVS.sdf + YosysVS/YosysVS.sln + YosysVS/YosysVS.v12.suo + +4. Zip YosysVS as YosysVS-Tpl-v1.zip + Checklist for adding internal cell types -- cgit v1.2.3 From c5dbb1aa28f5fb10ebbc0696545ede6fa76ce20b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Nov 2014 15:47:18 +0100 Subject: Minor corrections in CodingReadme --- CodingReadme | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 0e3ff6949..88f16ff0a 100644 --- a/CodingReadme +++ b/CodingReadme @@ -137,7 +137,7 @@ Update the CHANGELOG file: vi CHANGELOG -Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.6,release}": +Run all tests with "make config-{clang,gcc,gcc-4.6}": cd ~yosys make clean @@ -149,9 +149,8 @@ Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.6,release}": make full cd ~vloghammer - make purge - make gen_issues gen_samples - make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" FULL=1 world + make purge gen_issues gen_samples + make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world chromium-browser report.html -- cgit v1.2.3 From b9f2127f5d5a78bab74f511a71b6a369065a0383 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 8 Nov 2014 10:59:48 +0100 Subject: Various documentation updates --- CodingReadme | 1 + 1 file changed, 1 insertion(+) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 88f16ff0a..03de3fc17 100644 --- a/CodingReadme +++ b/CodingReadme @@ -159,6 +159,7 @@ Then with default config setting: cd ~yosys ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v + ./yosys -p 'synth; show' tests/simple/fiedler-cooley.v cd ~yosys make manual -- cgit v1.2.3 From eceecfeb8cf13f9afc200ab7eb7e93ff8f2acac4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Dec 2014 19:39:17 +0100 Subject: Added more information to CodingReadme --- CodingReadme | 116 +++++++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 110 insertions(+), 6 deletions(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 03de3fc17..bdadf821d 100644 --- a/CodingReadme +++ b/CodingReadme @@ -4,19 +4,123 @@ Getting Started =============== -Reading List ------------- +Outline of a Yosys command +-------------------------- + +Here is a the C++ code for a "hello_world" Yosys command (hello.cc): + + #include "kernel/yosys.h" + + USING_YOSYS_NAMESPACE + PRIVATE_NAMESPACE_BEGIN + + struct HelloWorldPass : public Pass { + HelloWorldPass() : Pass("hello_world") { } + virtual void execute(vector, Design*) { + log("Hello World!\n"); + } + } HelloWorldPass; + + PRIVATE_NAMESPACE_END + +This can be built into a Yosys module using the following command: + + yosys-config --exec --cxx --cxxflags --ldflags -o hello.so -shared hello.cc --ldlibs + +And then executed using the following command: + + yosys -m hello.so -p hello_world + + +Yosys Data Structures +--------------------- + +Here is a short list of data structures that you should make yourself familiar +with before you write C++ code for Yosys. The following data structures are all +defined when "kernel/yosys.h" is included and USING_YOSYS_NAMESPACE is used. + + 1. Yosys Container Classes + +Yosys uses dict and pool as main container classes. dict is +essentially a replacement for std::unordered_map and pool is +essentially a replacement for std::unordered_set. The main differences are: + + - dict and pool are about 2x faster than the std containers + + - references to elements in a dict or pool are invalidated by + insert operations (just like you are used from std::vector). + + - dict and pool will have the same order of iteration across + all compilers and architectures. + + 2. Standard STL data types -To write Yosys C++ code you need to know at least the following classes in kernel/rtlil.h: +In Yosys we use std::vector and std::string whenever applicable. When +dict and pool are not suitable then std::map and std::set +are used instead. + +The types std::vector and std::string are also available as vector +and string in the Yosys namespace. + + 3. RTLIL objects + +The current design (essentially a collection of modules, each defined by a +netlist) is stored in memory using RTLIL object (declared in kernel/rtlil.h, +automatically included by kernel/yosys.h). You should glance over at least +the declarations for the following types in kernel/rtlil.h: + + RTLIL::IdString + This is a handle for an identifier (e.g. cell or wire name). + It feels a lot like a std::string, but is only a single int + in size. (The actual string is stored in a global lookup + table.) + + RTLIL::SigBit + A single signal bit. I.e. either a constant (0, 1, x, z) or + a single bit from a wire. + + RTLIL::SigSpec + Essentially a vector of SigBits. RTLIL::Wire RTLIL::Cell + The building blocks of the netlist in a module. + RTLIL::Module - RTLIL::SigSpec + RTLIL::Design + The module is a container with connected cells and wires + in it. The design is a container with modules in it. + +All this types are also available without the RTLIL:: prefix in the Yosys +namespace. + + 4. SigMap and other Helper Classes + +There are a couple of additional helper classes that are in wide use +in Yosys. Most importantly there is SigMap (declared in kernel.sigtools.h). + +When a design has many wires in it that are connected to each other, then +a single signal bit can have multiple valid names. The SigMap object can +be used to map SigSpecs or SigBits to unique SigSpecs and SigBits that +consitently only uses one wire from a group of connected wires. For example: + + SigBit a = module->addWire(NEW_ID); + SigBit b = module->addWire(NEW_ID); + module->connect(a, b); + + log("%d\n", a == b); // will print 0 + + SigMap sigmap(module); + log("%d\n", sigmap(a) == sigmap(b)); // will print 1 + + +Example Code +------------ The following yosys commands are a good starting point if you are looking for examples of how to use the Yosys API: + manual/CHAPTER_Prog/stubnets.cc passes/opt/wreduce.cc passes/techmap/maccmap.cc @@ -25,7 +129,7 @@ Notes on the existing codebase ------------------------------ For historical reasons not all parts of Yosys adhere to the current coding -styles. When adding code to existing parts of the system, adhere to this guide +style. When adding code to existing parts of the system, adhere to this guide for the new code instead of trying to mimic the style of the surrounding code. @@ -62,7 +166,7 @@ gcc 4.6 is allowed in Yosys code. This will change in future releases. In general Yosys uses "int" instead of "size_t". To avoid compiler warnings for implicit type casts, always use "GetSize(foobar)" instead -of "foobar.size()". (GetSize() is defined by kernel/yosys.h) +of "foobar.size()". (GetSize() is defined in kernel/yosys.h) Use range-based for loops whenever applicable. -- cgit v1.2.3 From 539dd805f44ece3e39f4c68e4ea1bdc9b662e83f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 31 Dec 2014 14:26:54 +0100 Subject: Improvements in CodingReadme --- CodingReadme | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index bdadf821d..2349b2ee2 100644 --- a/CodingReadme +++ b/CodingReadme @@ -1,5 +1,10 @@ +This file contains some very brief documentation on things like programming APIs. +Also consult the Yosys manual and the section about programming in the presentation. +(Both can be downloaded as PDF from the yosys webpage.) + +--snip-- only the lines below this mark are included in the yosys manual --snip-- Getting Started =============== @@ -42,13 +47,21 @@ defined when "kernel/yosys.h" is included and USING_YOSYS_NAMESPACE is used. 1. Yosys Container Classes Yosys uses dict and pool as main container classes. dict is -essentially a replacement for std::unordered_map and pool is -essentially a replacement for std::unordered_set. The main differences are: +essentially a replacement for std::unordered_map and pool is a +replacement for std::unordered_set. The main characteristics are: - dict and pool are about 2x faster than the std containers - references to elements in a dict or pool are invalidated by - insert operations (just like you are used from std::vector). + insert and remove operations (similar to std::vector on push_back()). + + - some iterators are invalidated by erase(). specifically, iterators + that have not passed the erased element yet are invalidated. (erase() + itself returns valid iterator to the next element.) + + - no iterators are invalidated by insert(). elements are inserted at + begin(). i.e. only a new iterator that starts at begin() will see the + inserted elements. - dict and pool will have the same order of iteration across all compilers and architectures. @@ -97,12 +110,12 @@ namespace. 4. SigMap and other Helper Classes There are a couple of additional helper classes that are in wide use -in Yosys. Most importantly there is SigMap (declared in kernel.sigtools.h). +in Yosys. Most importantly there is SigMap (declared in kernel/sigtools.h). -When a design has many wires in it that are connected to each other, then -a single signal bit can have multiple valid names. The SigMap object can -be used to map SigSpecs or SigBits to unique SigSpecs and SigBits that -consitently only uses one wire from a group of connected wires. For example: +When a design has many wires in it that are connected to each other, then a +single signal bit can have multiple valid names. The SigMap object can be used +to map SigSpecs or SigBits to unique SigSpecs and SigBits that consitently +only use one wire from such a group of connected wires. For example: SigBit a = module->addWire(NEW_ID); SigBit b = module->addWire(NEW_ID); @@ -162,7 +175,7 @@ C++ Langugage ------------- Yosys is written in C++11. At the moment only constructs supported by -gcc 4.6 is allowed in Yosys code. This will change in future releases. +gcc 4.6 are allowed in Yosys code. This will change in future releases. In general Yosys uses "int" instead of "size_t". To avoid compiler warnings for implicit type casts, always use "GetSize(foobar)" instead @@ -171,6 +184,8 @@ of "foobar.size()". (GetSize() is defined in kernel/yosys.h) Use range-based for loops whenever applicable. +--snap-- only the lines above this mark are included in the yosys manual --snap-- + Creating the Visual Studio Template Project =========================================== -- cgit v1.2.3 From 1e08621e7e2c219169b3b6c5fe1d581052e4d429 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 31 Dec 2014 14:52:46 +0100 Subject: Added hashlib .count(key, iterator) and it1 < it2 --- CodingReadme | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 2349b2ee2..92d54d283 100644 --- a/CodingReadme +++ b/CodingReadme @@ -63,8 +63,14 @@ replacement for std::unordered_set. The main characteristics are: begin(). i.e. only a new iterator that starts at begin() will see the inserted elements. + - the method .count(key, iterator) is like .count(key) but only + considers elements that can be reached via the iterator. + + - iterators can be compared. it1 < it2 means that the position of t2 + can be reached via t1 but not vice versa. + - dict and pool will have the same order of iteration across - all compilers and architectures. + all compilers, standard libraries and architectures. 2. Standard STL data types -- cgit v1.2.3 From 0217ea0fb82b9170bb6efce734f1965ff2b181e7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 18 Jan 2015 12:12:33 +0100 Subject: Added hashlib::idict<> --- CodingReadme | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 92d54d283..78bc5a3ce 100644 --- a/CodingReadme +++ b/CodingReadme @@ -72,6 +72,20 @@ replacement for std::unordered_set. The main characteristics are: - dict and pool will have the same order of iteration across all compilers, standard libraries and architectures. +In addition to dict and pool there is also an idict that +creates a bijective map from K to the integers. For example: + + idict si; + log("%d\n", si("hello")); // will print 42 + log("%d\n", si("world")); // will print 43 + log("%d\n", si.at("world")); // will print 43 + log("%d\n", si.at("dummy")); // will throw exception + log("%s\n", si[42].c_str())); // will print hello + log("%s\n", si[43].c_str())); // will print world + log("%s\n", si[44].c_str())); // will throw exception + +It is not possible to remove elements from an idict. + 2. Standard STL data types In Yosys we use std::vector and std::string whenever applicable. When -- cgit v1.2.3 From 743da01e9ec7be4d6d7db293b49ef81048570251 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 7 Feb 2015 19:04:06 +0100 Subject: Improved building of plugins --- CodingReadme | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 78bc5a3ce..0b141cecd 100644 --- a/CodingReadme +++ b/CodingReadme @@ -319,6 +319,11 @@ Also with default config setting: bash example.sh +Test building plugins with various of the standard passes: + + yosys-config --build test.so equiv_simple.cc + + Finally if a current verific library is available: cd ~yosys -- cgit v1.2.3 From c3ce824af00beaaaa0065cb1056f61b567f979b1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 8 Feb 2015 12:01:00 +0100 Subject: Various updates to CodingReadme --- CodingReadme | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 0b141cecd..c509f6962 100644 --- a/CodingReadme +++ b/CodingReadme @@ -32,6 +32,10 @@ This can be built into a Yosys module using the following command: yosys-config --exec --cxx --cxxflags --ldflags -o hello.so -shared hello.cc --ldlibs +Or short: + + yosys-config --build hello.so hello.cc + And then executed using the following command: yosys -m hello.so -p hello_world @@ -69,6 +73,9 @@ replacement for std::unordered_set. The main characteristics are: - iterators can be compared. it1 < it2 means that the position of t2 can be reached via t1 but not vice versa. + - the method .sort() can be used to sort the elements in the container + the container stays sorted until elements are added or removed. + - dict and pool will have the same order of iteration across all compilers, standard libraries and architectures. @@ -109,8 +116,8 @@ the declarations for the following types in kernel/rtlil.h: table.) RTLIL::SigBit - A single signal bit. I.e. either a constant (0, 1, x, z) or - a single bit from a wire. + A single signal bit. I.e. either a constant state (0, 1, + x, z) or a single bit from a wire. RTLIL::SigSpec Essentially a vector of SigBits. @@ -134,7 +141,7 @@ in Yosys. Most importantly there is SigMap (declared in kernel/sigtools.h). When a design has many wires in it that are connected to each other, then a single signal bit can have multiple valid names. The SigMap object can be used -to map SigSpecs or SigBits to unique SigSpecs and SigBits that consitently +to map SigSpecs or SigBits to unique SigSpecs and SigBits that consistently only use one wire from such a group of connected wires. For example: SigBit a = module->addWire(NEW_ID); @@ -154,8 +161,7 @@ The following yosys commands are a good starting point if you are looking for ex of how to use the Yosys API: manual/CHAPTER_Prog/stubnets.cc - passes/opt/wreduce.cc - passes/techmap/maccmap.cc + manual/PRESENTATION_Prog/my_cmd.cc Notes on the existing codebase @@ -312,11 +318,8 @@ Also with default config setting: cd ~yosys/techlibs/cmos bash testbench.sh - cd ~yosys/techlibs/xilinx/example_sim_counter - bash run_sim.sh - - cd ~yosys/techlibs/xilinx/example_mojo_counter - bash example.sh + cd ~yosys/techlibs/xilinx/example_basys3 + bash run.sh Test building plugins with various of the standard passes: -- cgit v1.2.3 From 0fcc8c14674aecf6cf327740e6081bf722d806f6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 8 Feb 2015 15:13:51 +0100 Subject: Minor "make vgtest" changes --- CodingReadme | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index c509f6962..5769c85f9 100644 --- a/CodingReadme +++ b/CodingReadme @@ -286,7 +286,8 @@ Run all tests with "make config-{clang,gcc,gcc-4.6}": cd ~yosys make clean - make test vloghtb + make test + make vloghtb make install cd ~yosys-bigsim @@ -301,6 +302,9 @@ Run all tests with "make config-{clang,gcc,gcc-4.6}": Then with default config setting: + cd ~yosys + make vgtest + cd ~yosys ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v -- cgit v1.2.3 From 139648554dbdfbd9cdeab6736f88914a122fb70a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 8 Feb 2015 23:30:15 +0100 Subject: CodingReadme update --- CodingReadme | 1 + 1 file changed, 1 insertion(+) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 5769c85f9..46624e9c7 100644 --- a/CodingReadme +++ b/CodingReadme @@ -309,6 +309,7 @@ Then with default config setting: ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v ./yosys -p 'synth; show' tests/simple/fiedler-cooley.v + ./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v cd ~yosys make manual -- cgit v1.2.3 From a779a09771f7373b8d1e77d7a9182fd3ed9008e5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 9 Feb 2015 13:24:29 +0100 Subject: Fixed creation of command reference in manual --- CodingReadme | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 46624e9c7..f4924dfb2 100644 --- a/CodingReadme +++ b/CodingReadme @@ -282,6 +282,14 @@ Update the CHANGELOG file: vi CHANGELOG +Update command reference in manual: + + cd ~yosys + make + cd manual + ../yosys -p 'help -write-tex-command-reference-manual' + + Run all tests with "make config-{clang,gcc,gcc-4.6}": cd ~yosys -- cgit v1.2.3 From 68979d13957825b2d9ec7638f5af057a3c832f89 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 9 Feb 2015 16:36:37 +0100 Subject: Various changes to release checklist --- CodingReadme | 70 ++++++++++++++++++++++-------------------------------------- 1 file changed, 25 insertions(+), 45 deletions(-) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index f4924dfb2..1cee94e81 100644 --- a/CodingReadme +++ b/CodingReadme @@ -282,30 +282,18 @@ Update the CHANGELOG file: vi CHANGELOG -Update command reference in manual: +Update and check documentation: cd ~yosys - make - cd manual - ../yosys -p 'help -write-tex-command-reference-manual' - - -Run all tests with "make config-{clang,gcc,gcc-4.6}": + make update-manual + make manual + - sanity check the figures in the appnotes and presentation + - if there are any odd things -> investigate + - make cosmetic changes to the .tex files if necessary cd ~yosys - make clean - make test - make vloghtb - make install - - cd ~yosys-bigsim - make clean - make full - - cd ~vloghammer - make purge gen_issues gen_samples - make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world - chromium-browser report.html + vi README CodingReadme + - is the information provided in those file still up to date Then with default config setting: @@ -319,15 +307,6 @@ Then with default config setting: ./yosys -p 'synth; show' tests/simple/fiedler-cooley.v ./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v - cd ~yosys - make manual - - sanity check the figures in the appnotes and presentation - - if there are any odd things -> investigate - - make cosmetic changes to the .tex files if necessary - - -Also with default config setting: - cd ~yosys/techlibs/cmos bash testbench.sh @@ -338,9 +317,10 @@ Also with default config setting: Test building plugins with various of the standard passes: yosys-config --build test.so equiv_simple.cc + - also check the code examples in CodingReadme -Finally if a current verific library is available: +And if a version of the verific library is currently available: cd ~yosys cat frontends/verific/build_amd64.txt @@ -350,12 +330,22 @@ Finally if a current verific library is available: ../../yosys test_navre.ys -Release candiate: +Finally run all tests with "make config-{clang,gcc,gcc-4.6}": + + cd ~yosys + make clean + make test + make vloghtb + make install + + cd ~yosys-bigsim + make clean + make full - - create branch yosys-x.y.z-rc and push to github - - contact the usual suspects per mail and ask them to test - - post on the reddit and ask people to test - - commit KISS fixes to the -rc branch if necessary + cd ~vloghammer + make purge gen_issues gen_samples + make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world + chromium-browser report.html Release: @@ -367,7 +357,6 @@ Release: - push tag to github - post changelog on github - post short release note on reddit - - delete -rc branch from github Updating the website: @@ -384,12 +373,3 @@ Updating the website: git commit -am update make push - -In master branch: - - git merge {release-tag} - - set version to x.y.z+ in Makefile - - add section "Yosys x.y.z .. x.y.z+" to CHANGELOG - git commit --amend -am "Yosys x.y.z+" - - -- cgit v1.2.3 From 138547f41b5851abd7631074b1dbc3d6ef3fb4b3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 17 Feb 2015 13:01:01 +0100 Subject: CodingReadme --- CodingReadme | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'CodingReadme') diff --git a/CodingReadme b/CodingReadme index 1cee94e81..54ea368e7 100644 --- a/CodingReadme +++ b/CodingReadme @@ -154,6 +154,41 @@ only use one wire from such a group of connected wires. For example: log("%d\n", sigmap(a) == sigmap(b)); // will print 1 +Using the RTLIL Netlist Format +------------------------------ + +In the RTLIL netlist format the cell ports contain SigSpecs that point to the +Wires. There are no references in the other direction. This has two direct +consequences: + +(1) It is very easy to go from cells to wires but hard to go in the other way. + +(2) There is no danger in removing cells from the netlists, but removing wires +can break the netlist format when there are still references to the wire +somewhere in the netlist. + +The solution to (1) is easy: Create custom indexes that allow you to make fast +lookups for the wire-to-cell direction. You can either use existing generic +index structures to do that (such as the ModIndex class) or write your own +index. For many application it is simplest to construct a custom index. For +example: + + SigMap sigmap(module); + dict sigbit_to_driver_index; + + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) + if (cell->output(conn.first)) + for (auto bit : sigmap(conn.second)) + sigbit_to_driver_index[bit] = cell; + +Regarding (2): There is a general theme in Yosys that you don't remove wires +from the design. You can rename them, unconnect them, but you do not actually remove +the Wire object from the module. Instead you let the "clean" command take care +of the dangling wires. On the other hand it is safe to remove cells (as long as +you make sure this does not invalidate a custom index you are using in your code). + + Example Code ------------ -- cgit v1.2.3