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|
-- GHDL Run Time (GRT) - FST generator.
-- Copyright (C) 2014 Tristan Gingold
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <gnu.org/licenses>.
--
-- As a special exception, if other files instantiate generics from this
-- unit, or you link this unit with other files to produce an executable,
-- this unit does not by itself cause the resulting executable to be
-- covered by the GNU General Public License. This exception does not
-- however invalidate any other reasons why the executable file might be
-- covered by the GNU Public License.
-------------------------------------------------------------------------------
-- TODO:
-- * Fix the following issues :
-- + Currently both the top level signals and signals in packages aren't
-- visible on the tree view (SST) of gtkwave, but both of them are visible
-- when no item is selected in the tree view and are mixed together.
-- (Same issue with VCD waves.)
-- + After calling FST_Put_Hierarchy (Pack, Match_List), Avhpi_Error is
-- raised several times when no signal paths are provided in a wave option
-- file. It has no consequences other than a printed message.
-- (Same issue with VCD waves.)
-- + Integer signals aren't displayed correctly but only their lowest bit is
-- shown.
with Ada.Unchecked_Deallocation;
with Interfaces; use Interfaces;
with Interfaces.C;
with Grt.Types; use Grt.Types;
with Grt.Vhdl_Types; use Grt.Vhdl_Types;
with Grt.Fst_Api; use Grt.Fst_Api;
with Grt.Vcd; use Grt.Vcd;
with Grt.Avhpi; use Grt.Avhpi;
with Grt.Errors; use Grt.Errors;
with Grt.Signals; use Grt.Signals;
with Grt.Table;
with Grt.Astdio; use Grt.Astdio;
with Grt.Hooks; use Grt.Hooks;
with Grt.Rtis; use Grt.Rtis;
with Grt.Rtis_Types; use Grt.Rtis_Types;
with Grt.To_Strings;
with Grt.Wave_Opt; use Grt.Wave_Opt;
with Grt.Wave_Opt.Design; use Grt.Wave_Opt.Design;
with Grt.Options;
pragma Elaborate_All (Grt.Table);
package body Grt.Fst is
-- FST format has a mechanism to declare signal aliases (if two signals
-- in the hierarchy are the same). Enabling this reduce the number of
-- signals dumped, but weirdly it makes the FST file slightly bigger.
Flag_Aliases : constant Boolean := False;
-- Global FST context. Set to non-NULL iff dumping signals to an FST file.
Context : fstContext := Null_fstContext;
-- Index type of the table of vcd variables to dump.
type Fst_Index_Type is new Integer;
-- Return TRUE if OPT is an option for FST.
function Fst_Option (Opt : String) return Boolean
is
F : constant Natural := Opt'First;
Fst_Filename : String_Access;
begin
if Opt'Length < 6 or else Opt (F .. F + 5) /= "--fst=" then
return False;
end if;
if Context /= Null_fstContext then
Error ("--fst: file already set");
return True;
end if;
-- Add an extra NUL character.
Fst_Filename := new String (1 .. Opt'Length - 6 + 1);
Fst_Filename (1 .. Opt'Length - 6) := Opt (F + 6 .. Opt'Last);
Fst_Filename (Fst_Filename'Last) := NUL;
Context := fstWriterCreate
(To_Ghdl_C_String (Fst_Filename.all'Address), 1);
if Context = Null_fstContext then
Error_S ("fst: cannot open ");
Error_E (Fst_Filename (Fst_Filename'First .. Fst_Filename'Last - 1));
end if;
return True;
end Fst_Option;
procedure Fst_Help is
begin
Put_Line (" --fst=FILENAME dump signal values into an FST file");
end Fst_Help;
-- Called before elaboration.
procedure Fst_Init
is
Version : constant String := "GHDL FST v0" & NUL;
begin
if Context = Null_fstContext then
return;
end if;
fstWriterSetFileType (Context, FST_FT_VHDL);
fstWriterSetPackType (Context, FST_WR_PT_LZ4);
fstWriterSetTimescale (Context, -3 * Options.Time_Resolution_Scale);
fstWriterSetVersion (Context, To_Ghdl_C_String (Version'Address));
fstWriterSetRepackOnClose (Context, 1);
fstWriterSetParallelMode (Context, 0);
end Fst_Init;
type Fst_Sig_Info is record
Wire : Verilog_Wire_Info;
Hand : fstHandle;
end record;
package Fst_Table is new Grt.Table
(Table_Component_Type => Fst_Sig_Info,
Table_Index_Type => Fst_Index_Type,
Table_Low_Bound => 0,
Table_Initial => 32);
procedure Avhpi_Error (Err : AvhpiErrorT)
is
pragma Unreferenced (Err);
begin
Put_Line ("Fst.Avhpi_Error!");
end Avhpi_Error;
function Equal (Left, Right : Verilog_Wire_Info) return Boolean
is
Len : Ghdl_Index_Type;
begin
if Left.Vtype /= Right.Vtype
or else Left.Val /= Right.Val
then
return False;
end if;
-- Get length.
Len := Get_Wire_Length (Left);
if Len /= Get_Wire_Length (Right) then
return False;
end if;
-- Compare signals.
for I in 1 .. Len loop
if To_Signal_Arr_Ptr (Left.Ptr)(I - 1)
/= To_Signal_Arr_Ptr (Right.Ptr)(I - 1)
then
return False;
end if;
end loop;
return True;
end Equal;
function Hash (El : Verilog_Wire_Info) return Ghdl_Index_Type
is
Len : constant Ghdl_Index_Type := Get_Wire_Length (El);
Res : Ghdl_Index_Type;
Iaddr : Integer_Address;
begin
Res := Vcd_Var_Type'Pos (El.Vtype) * 2 + Vcd_Value_Kind'Pos (El.Val);
Res := Res + Len * 29;
for I in 1 .. Len loop
Iaddr := To_Integer (To_Signal_Arr_Ptr (El.Ptr)(I - 1).all'Address);
Res := Res +
Ghdl_Index_Type (Iaddr mod Integer_Address (Ghdl_Index_Type'Last));
end loop;
return Res;
end Hash;
-- Very simple hash table to detect aliases.
type Bucket_Type;
type Bucket_Acc is access Bucket_Type;
type Bucket_Type is record
El : Fst_Index_Type;
Next : Bucket_Acc;
end record;
type Hash_Table is array (Ghdl_Index_Type range <>) of Bucket_Acc;
type Hash_Table_Acc is access Hash_Table;
Hash_Tab : Hash_Table_Acc;
procedure Free_Hash_Tab
is
procedure Free_Hash_Table is new
Ada.Unchecked_Deallocation (Hash_Table, Hash_Table_Acc);
procedure Free_Bucket_Type is new
Ada.Unchecked_Deallocation (Bucket_Type, Bucket_Acc);
Ent, Nent : Bucket_Acc;
begin
for I in Hash_Tab'Range loop
Ent := Hash_Tab (I);
while Ent /= null loop
Nent := Ent.Next;
Free_Bucket_Type (Ent);
Ent := Nent;
end loop;
end loop;
Free_Hash_Table (Hash_Tab);
end Free_Hash_Tab;
procedure Fst_Add_Signal (Sig : VhpiHandleT)
is
Sig_Typemark, Sig_Subtype, Sig_Base_Type : VhpiHandleT;
Err : AvhpiErrorT;
Vcd_El : Verilog_Wire_Info;
Vt : fstVarType;
Sdt : fstSupplementalDataType;
Dir : fstVarDir;
Len : Interfaces.C.unsigned;
Name : String (1 .. 128);
Name_Len : Natural;
Type_Name : String (1 .. 32);
Type_Name_Len : Natural;
|
