From c529d4fc53ddbb96dd98f5d5fef37b4b5caa1896 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Nov 2014 13:34:05 +0100 Subject: Changelog for Yosys 0.4 --- CHANGELOG | 87 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 9 deletions(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 356957297..9821be86f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -3,13 +3,82 @@ List of changes and major improvements between releases ======================================================= -Yosys 0.3.0 .. Yoys 0.3.0+ --------------------------- - - ... TBD ... - - -Yosys 0.2.0 .. Yoys 0.3.0 +Yosys 0.3.0 .. Yosys 0.4 +------------------------ + + * Platform Support + - Added support for mxe-based cross-builds for win32 + - Added sourcecode-export as VisualStudio project + - Added experimental EMCC (JavaScript) support + + * Verilog Frontend + - Added -sv option for SystemVerilog (and automatic *.sv file support) + - Added support for real-valued constants and constant expressions + - Added support for non-standard "via_celltype" attribute on task/func + - Added support for non-standard "module mod_name(...);" syntax + - Added support for non-standard """ macro bodies + - Added support for array with more than one dimension + - Added support for $readmemh and $readmemb + - Added support for DPI functions + + * Changes in internal cell library + - Added $shift and $shiftx cell types + - Added $alu, $lcu, $fa and $macc cell types + - Removed $bu0 and $safe_pmux cell types + - $mem/$memwr WR_EN input is now a per-data-bit enable signal + - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ + - Renamed ports of $lut cells (from I->O to A->Y) + - Renamed $_INV_ to $_NOT_ + + * Changes for simple synthesis flows + - There is now a "synth" command with a recommended default script + - Many improvements in synthesis of arithmetic functions to gates + - Multiplieres and adders with many operands are using carry-save adder trees + - Remaining adders are now implemented using Brent–Kung carry look-ahead adders + - Various new high-level optimizations on RTL netlist + - Various improvements in FSM optimization + - Updated ABC to hg 930a4de962a1 (from 2014-10-14) + + * Changes in internal APIs and RTLIL + - Added log_id() and log_cell() helper functions + - Added function-like cell creation helpers + - Added GetSize() function (like .size() but with int) + - Major refactoring of RTLIL::Module and related classes + - Major refactoring of RTLIL::SigSpec and related classes + - Now RTLIL::IdString is essentially an int + - Added macros for code coverage counters + - Added some Makefile magic for pretty make logs + - Added "kernel/yosys.h" with all the core definitions + - Chanded a lot of code from FILE* to c++ streams + - Added RTLIL::Monitor API and "trace" command + - Added "Yosys" C++ namespace + + * Changes relevant to SAT solving + - Added ezSAT::keep_cnf() and ezSAT::non_incremental() + - Added native ezSAT support for vector shift ops + - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25) + + * New commands (or large improvements to commands) + - Added "synth" command with default script + - Added "share" (finally some real resource sharing) + - Added "memory_share" (reduce number of ports on memories) + - Added "wreduce" and "alumacc" commands + - Added "opt -keepdc -fine -full -fast" + - Added some "test_*" commands + + * Various other changes + - Added %D and %c select operators + - Added support for labels in yosys scripts + - Added support for here-documents in yosys scripts + - Support "+/" prefix for files from proc_share_dir + - Added "autoidx" statement to ilang language + - Switched from "yosys-svgviewer" to "xdot" + - Renamed "stdcells.v" to "techmap.v" + - Various bug fixes and small improvements + - Improved welcome and bye messages + + +Yosys 0.2.0 .. Yosys 0.3.0 -------------------------- * Driver program and overall behavior: @@ -59,8 +128,8 @@ Yosys 0.2.0 .. Yoys 0.3.0 - Various build fixes for OSX (Darwin) and OpenBSD -Yosys 0.1.0 .. Yoys 0.2.0 -------------------------- +Yosys 0.1.0 .. Yosys 0.2.0 +-------------------------- * Changes to the driver program: - Added "yosys -h" and "yosys -H" -- cgit v1.2.3 From 4f4d729e02babd32ebf56de3e87408e05c5728bc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Nov 2014 14:39:49 +0100 Subject: Updated ABC to 5b5af75f1dda --- CHANGELOG | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 9821be86f..8679d6c87 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -37,7 +37,7 @@ Yosys 0.3.0 .. Yosys 0.4 - Remaining adders are now implemented using Brent–Kung carry look-ahead adders - Various new high-level optimizations on RTL netlist - Various improvements in FSM optimization - - Updated ABC to hg 930a4de962a1 (from 2014-10-14) + - Updated ABC to hg 5b5af75f1dda (from 2014-11-07) * Changes in internal APIs and RTLIL - Added log_id() and log_cell() helper functions -- cgit v1.2.3 From 73f5ffcce84299193930e7f580f2cc9367633ab5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 8 Nov 2014 12:20:58 +0100 Subject: Now we are in Yoys 0.4+ development --- CHANGELOG | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 8679d6c87..5c0626403 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,8 +1,14 @@ -List of changes and major improvements between releases +List of major changes and improvements between releases ======================================================= +Yosys 0.4 .. Yosys 0.4+ +----------------------- + + ... TBD ... + + Yosys 0.3.0 .. Yosys 0.4 ------------------------ -- cgit v1.2.3 From b10f0088d1f598294bba7e86e6be2855dc529182 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 8 Feb 2015 12:01:22 +0100 Subject: Added Yosys 0.5 Changelog --- CHANGELOG | 50 ++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 4 deletions(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 5c0626403..9e980c75b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -3,10 +3,52 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.4 .. Yosys 0.4+ ------------------------ - - ... TBD ... +Yosys 0.4 .. Yosys 0.5 +---------------------- + + * API changes + - Added log_warning() + - Added cell->known(), cell->input(portname), cell->output(portname) + - Skip blackbox modules in design->selected_modules() + - Replaced std::map<> and std::set<> with dict<> and pool<> + - New SigSpec::extend() is what used to be SigSpec::extend_u0() + - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN + + * Cell library changes + - Added flip-flops with enable ($dffe etc.) + - Added $equiv cells for equivalence checking framework + + * Various + - Updated ABC to hg rev 61ad5f908c03 + - Added clock domain partitioning to ABC pass + - Improved plugin building (see "yosys-config --build") + - Added ENABLE_NDEBUG Makefile flag for high-performance builds + - Added "yosys -d", "yosys -L" and other driver improvements + - Added support for multi-bit (array) cell ports to "write_edif" + - Now printing most output to stdout, not stderr + - Added "onehot" attribute (set by "fsm_map") + - Various performance improvements + - Vastly improved Xilinx flow + - Added "make unsintall" + + * Equivalence checking + - Added equivalence checking commands: + equiv_make equiv_simple equiv_status + equiv_induct equiv_miter + equiv_add equiv_remove + + * Block RAM support: + - Added "memory_bram" command + - Added BRAM support to Xilinx flow + + * Other New Commands and Options + - Added "dff2dffe" + - Added "fsm -encfile" + - Added "dfflibmap -prepare" + - Added "write_blid -unbuf -undef -blackbox" + - Added "write_smt2" for writing SMT-LIBv2 files + - Added "test_cell -w -muxdiv" + - Added "select -read" Yosys 0.3.0 .. Yosys 0.4 -- cgit v1.2.3 From 183d4f8e711e0de91187b33b828144e482b6c94f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 8 Feb 2015 21:14:52 +0100 Subject: Added new APIs to changelog --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 9e980c75b..3efbe1093 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -8,6 +8,7 @@ Yosys 0.4 .. Yosys 0.5 * API changes - Added log_warning() + - Added eval_select_args() and eval_select_op() - Added cell->known(), cell->input(portname), cell->output(portname) - Skip blackbox modules in design->selected_modules() - Replaced std::map<> and std::set<> with dict<> and pool<> -- cgit v1.2.3