From 7a9031c48ed91de674f4ad1507b1148153930d0d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:22:53 -0700 Subject: Add CHANGELOG entry --- CHANGELOG | 2 ++ 1 file changed, 2 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index ca42df71e..92456df99 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -27,6 +27,8 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "opt_share" pass, run as part of "opt -full" - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping - Removed "ice40_unlut" + - Added "xilinx_srl" for Xilinx shift register extraction + - Removed "shregmap -tech xilinx" Yosys 0.8 .. Yosys 0.8-dev -------------------------- -- cgit v1.2.3 From cee30deef5f48b97af961ecb6f7194eac14d891c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 12:24:25 -0700 Subject: Mention shregmap -tech xilinx is superseded --- CHANGELOG | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index b4b3005d4..5848ae705 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -29,7 +29,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Removed "ice40_unlut" - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - - Removed "shregmap -tech xilinx" + - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") Yosys 0.8 .. Yosys 0.8-dev -------------------------- -- cgit v1.2.3