From 04153c501128ae37c7ed1235266ab6b32902b878 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 16:14:26 -0700 Subject: Update CHANGELOG --- CHANGELOG | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index c29429295..f0a0d0fae 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -38,6 +38,11 @@ Yosys 0.9 .. Yosys 0.9-dev - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") + - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones + - Added "xilinx_dsp" for Xilinx DSP packing + - "synth_xilinx" to now infer DSP blocks (-nodsp to disable) + - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) + - "synth_ice40 -dsp" to infer DSP blocks Yosys 0.8 .. Yosys 0.9 ---------------------- -- cgit v1.2.3 From 0020a18929c30744eae4960ab97f6ebefc32a154 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 12:00:39 -0700 Subject: Add more entries --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 8d7dd3e19..8ee73771f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -41,6 +41,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass - Added "-match-init" option to "dff2dffs" pass - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones + - Added "ice40_dsp" for Lattice iCE40 DSP packing - Added "xilinx_dsp" for Xilinx DSP packing - "synth_xilinx" to now infer DSP blocks (-nodsp to disable) - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) -- cgit v1.2.3