From 4fadcc8f25d5ef1e494aa7d5e49d893afdaa1705 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 20 Jan 2021 08:49:32 -0700
Subject: verilog: allow spaces in macro arguments
---
frontends/verilog/preproc.cc | 1 -
tests/simple/macro_arg_spaces.sv | 28 ++++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
create mode 100644 tests/simple/macro_arg_spaces.sv
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 752f7a7a8..5a2804a41 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -392,7 +392,6 @@ static bool read_argument(std::string &dest)
{
std::vector<char> openers;
for (;;) {
- skip_spaces();
std::string tok = next_token(true);
if (tok == ")") {
if (openers.empty())
diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv
new file mode 100644
index 000000000..75c4cd136
--- /dev/null
+++ b/tests/simple/macro_arg_spaces.sv
@@ -0,0 +1,28 @@
+module top(
+ input wire [31:0] i,
+ output wire [31:0] x, y, z
+);
+
+`define BAR(a) a
+`define FOO(a = function automatic [31:0] f) a
+
+`BAR(function automatic [31:0] a);
+ input [31:0] i;
+ a = i * 2;
+endfunction
+
+`FOO();
+ input [31:0] i;
+ f = i * 3;
+endfunction
+
+`FOO(function automatic [31:0] b);
+ input [31:0] i;
+ b = i * 5;
+endfunction
+
+assign x = a(i);
+assign y = f(i);
+assign z = b(i);
+
+endmodule
--
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