From ff9f1fb86e41eb59a92590efe03423f15a3d9cc0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 18 Mar 2023 18:11:50 +0100 Subject: Start unification effort for machxo2 and ecp5 --- techlibs/machxo2/Makefile.inc | 1 + techlibs/machxo2/cells_map.v | 8 ++------ techlibs/machxo2/cells_sim.v | 39 +++++++++++++++++---------------------- techlibs/machxo2/synth_machxo2.cc | 6 +++--- 4 files changed, 23 insertions(+), 31 deletions(-) diff --git a/techlibs/machxo2/Makefile.inc b/techlibs/machxo2/Makefile.inc index f6aafbd2b..acc32659d 100644 --- a/techlibs/machxo2/Makefile.inc +++ b/techlibs/machxo2/Makefile.inc @@ -1,6 +1,7 @@ OBJS += techlibs/machxo2/synth_machxo2.o +$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/cells_io.vh)) $(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v)) $(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v)) diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v index 9c370f246..33328df5f 100644 --- a/techlibs/machxo2/cells_map.v +++ b/techlibs/machxo2/cells_map.v @@ -25,10 +25,6 @@ module \$lut (A, Y); endmodule // DFFs -module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule -// IO- "$__" cells for the iopadmap pass. -module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b0)); endmodule -module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule -module \$__FACADE_TOUTPAD (input I, T, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(T)); endmodule -module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(T)); endmodule +`include "cells_io.vh" diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 82c9d8c4b..86fc0cd8e 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -11,7 +11,7 @@ module LUT4 #( assign Z = A ? s1[1] : s1[0]; endmodule -module FACADE_FF #( +module TRELLIS_FF #( parameter GSR = "ENABLED", parameter CEMUX = "1", parameter CLKMUX = "0", @@ -77,7 +77,7 @@ endmodule /* For consistency, input order matches TRELLIS_SLICE even though the BELs in prjtrellis were filled in clockwise order from bottom left. */ -module FACADE_SLICE #( +module TRELLIS_SLICE #( parameter MODE = "LOGIC", parameter GSR = "ENABLED", parameter SRMODE = "LSR_OVER_CE", @@ -139,33 +139,34 @@ module FACADE_SLICE #( endgenerate /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F - outputs (in other words, feeds back into FACADE_SLICE). */ + outputs (in other words, feeds back into TRELLIS_SLICE). */ wire di0 = (REG0_SD == "1") ? DI0 : M0; wire di1 = (REG1_SD == "1") ? DI1 : M1; - FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), + TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET), .REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0)); - FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), + TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET), .REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1)); endmodule -module FACADE_IO #( +module TRELLIS_IO #( parameter DIR = "INPUT" ) ( - inout PAD, + (* iopad_external_pin *) + inout B, input I, T, output O ); generate if (DIR == "INPUT") begin - assign O = PAD; + assign O = B; end else if (DIR == "OUTPUT") begin - assign PAD = T ? 1'bz : I; + assign B = T ? 1'bz : I; end else if (DIR == "BIDIR") begin - assign PAD = T ? 1'bz : I; - assign O = PAD; + assign B = T ? 1'bz : I; + assign O = B; end else begin ERROR_UNKNOWN_IO_MODE error(); end @@ -320,14 +321,8 @@ module DP8KC( parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; endmodule -// IO- "$__" cells for the iopadmap pass. These are temporary cells not meant -// to be instantiated by the end user. They are required in this file for -// attrmvcp to work. -(* blackbox *) -module \$__FACADE_OUTPAD (input I, output O); endmodule -(* blackbox *) -module \$__FACADE_INPAD (input I, output O); endmodule -(* blackbox *) -module \$__FACADE_TOUTPAD (input I, T, output O); endmodule -(* blackbox *) -module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); endmodule +`ifndef NO_INCLUDES + +`include "cells_io.vh" + +`endif diff --git a/techlibs/machxo2/synth_machxo2.cc b/techlibs/machxo2/synth_machxo2.cc index dbd01bbfd..4ca6351bd 100644 --- a/techlibs/machxo2/synth_machxo2.cc +++ b/techlibs/machxo2/synth_machxo2.cc @@ -214,9 +214,9 @@ struct SynthMachXO2Pass : public ScriptPass { if (!noiopad || help_mode) { - run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD ~T:I:O -tinoutpad $__FACADE_TINOUTPAD ~T:O:I:B A:top"); - run("attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]"); - run("attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]"); + run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')"); + run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]"); + run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); } } -- cgit v1.2.3