From 817ac7c5e051b2f0947bd9cb9044ac7c3e2f089c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 14:17:45 -0700 Subject: Fix UB --- passes/pmgen/peepopt_dffmux.pmg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index 60a708616..fbabf90f0 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -35,8 +35,8 @@ match cemux endmatch code - SigSpec &D = cemux->connections_.at(cemuxAB == \A ? \B : \A); - SigSpec &Q = dff->connections_.at(\Q); + SigSpec D = port(cemux, cemuxAB == \A ? \B : \A); + SigSpec Q = port(dff, \Q); Const rst; if (rstmux) rst = port(rstmux, rstmuxBA).as_const(); -- cgit v1.2.3 From 3a49aa6b4a707f558ec378a25d28c3e0d914cfac Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 14:20:49 -0700 Subject: Tidy up --- passes/pmgen/peepopt_dffmux.pmg | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index fbabf90f0..c88a52226 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -42,6 +42,12 @@ code rst = port(rstmux, rstmuxBA).as_const(); int width = GetSize(D); + SigSpec &ceA = cemux->connections_.at(\A); + SigSpec &ceB = cemux->connections_.at(\B); + SigSpec &ceY = cemux->connections_.at(\Y); + SigSpec &dffD = dff->connections_.at(\D); + SigSpec &dffQ = dff->connections_.at(\Q); + if (D[width-1] == D[width-2]) { did_something = true; @@ -61,12 +67,12 @@ code } } - cemux->connections_.at(\A).remove(i, width-i); - cemux->connections_.at(\B).remove(i, width-i); - cemux->connections_.at(\Y).remove(i, width-i); + ceA.remove(i, width-i); + ceB.remove(i, width-i); + ceY.remove(i, width-i); cemux->fixup_parameters(); - dff->connections_.at(\D).remove(i, width-i); - dff->connections_.at(\Q).remove(i, width-i); + dffD.remove(i, width-i); + dffQ.remove(i, width-i); dff->fixup_parameters(); log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i); @@ -88,11 +94,11 @@ code if (init == State::Sx || init == D[i].data) { count++; module->connect(Q[i], D[i]); - cemux->connections_.at(\A).remove(i); - cemux->connections_.at(\B).remove(i); - cemux->connections_.at(\Y).remove(i); - dff->connections_.at(\D).remove(i); - dff->connections_.at(\Q).remove(i); + ceA.remove(i); + ceB.remove(i); + ceY.remove(i); + dffD.remove(i); + dffQ.remove(i); } } if (count > 0) { -- cgit v1.2.3 From 14d72c39c385bba3005085815a0d66989a437eff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 16:33:18 -0700 Subject: Revert "Make one check $shift(x)? only; change testcase to be 8b" This reverts commit e2c2d784c8217e4bcf29fb6b156b6a8285036b80. --- passes/pmgen/peepopt_shiftmul.pmg | 5 ++--- tests/various/peepopt.ys | 4 ++-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg index e1da52182..d4748ae19 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul.pmg @@ -50,9 +50,8 @@ code if (GetSize(const_factor_cnst) > 20) reject; - if (shift->type.in($shift, $shiftx)) - if (GetSize(port(shift, \Y)) > const_factor) - reject; + if (GetSize(port(shift, \Y)) > const_factor) + reject; int factor_bits = ceil_log2(const_factor); SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A); diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 886c8cd9d..abee9cc0a 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D design -reset read_verilog <> (w * (8'b110)); +assign y = 1'b1 >> (w * (3'b110)); endmodule EOT @@ -25,7 +25,7 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr -select -assert-count 0 t:$mul +select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### -- cgit v1.2.3 From a2eee9ebefc6e8089c815b4355bc64d1ac3396b5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 16:41:10 -0700 Subject: Add counter-example from @cliffordwolf --- tests/various/peepopt.ys | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index abee9cc0a..7c1c3b5bc 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -30,6 +30,30 @@ select -assert-count 0 t:$shr t:$mul %% t:* %D #################### +design -reset +read_verilog <> (S*3); +endmodule +EOT + +prep +design -save gold +peepopt +design -stash gate + +design -import gold -as gold peepopt_shiftmul_2 +design -import gate -as gate peepopt_shiftmul_2 + +miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter +sat -show-public -enable_undef -prove-asserts miter +select -assert-count 1 t:$shr +select -assert-count 1 t:$mul +select -assert-count 0 t:$shr t:$mul %% t:* %D +exit + +#################### + design -reset read_verilog < Date: Fri, 13 Sep 2019 18:19:07 -0700 Subject: Oops --- tests/various/peepopt.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 7c1c3b5bc..6bca62e2b 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -47,10 +47,10 @@ design -import gate -as gate peepopt_shiftmul_2 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter sat -show-public -enable_undef -prove-asserts miter +cd gate select -assert-count 1 t:$shr select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D -exit #################### -- cgit v1.2.3