From e9dede01ca8834ea3c211862a5d6c0119b2b578a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 24 Oct 2013 11:27:30 +0200
Subject: Fixed handling of boolean attributes (backends)

---
 backends/autotest/autotest.cc       | 6 +++---
 backends/blif/blif.cc               | 2 +-
 backends/edif/edif.cc               | 6 +++---
 backends/intersynth/intersynth.cc   | 2 +-
 backends/spice/spice.cc             | 2 +-
 backends/verilog/verilog_backend.cc | 2 +-
 6 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index f9c6d364f..6fd3a43cd 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -109,7 +109,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
 				fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
 			} else if (wire->port_input) {
 				count_ports++;
-				bool is_clksignal = wire->attributes.count("\\gentb_clock") > 0;
+				bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
 				for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); it3++)
 				for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); it4++) {
 					if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
@@ -120,11 +120,11 @@ static void autotest(FILE *f, RTLIL::Design *design)
 							is_clksignal = true;
 					}
 				}
-				if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
+				if (is_clksignal && !wire->get_bool_attribute("\\gentb_constant")) {
 					signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
 				} else {
 					signal_in[idy("sig", mod->name, wire->name)] = wire->width;
-					if (wire->attributes.count("\\gentb_constant") > 0)
+					if (wire->get_bool_attribute("\\gentb_constant"))
 						signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
 				}
 				fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index f87880616..747ba17d3 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -298,7 +298,7 @@ struct BlifBackend : public Backend {
 		for (auto module_it : design->modules)
 		{
 			RTLIL::Module *module = module_it.second;
-			if ((module->attributes.count("\\placeholder") > 0) > 0)
+			if ((module->get_bool_attribute("\\placeholder")) > 0)
 				continue;
 
 			if (module->processes.size() != 0)
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 4e38029a9..f898dc6d7 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -118,7 +118,7 @@ struct EdifBackend : public Backend {
 		for (auto module_it : design->modules)
 		{
 			RTLIL::Module *module = module_it.second;
-			if ((module->attributes.count("\\placeholder") > 0) > 0)
+			if (module->get_bool_attribute("\\placeholder"))
 				continue;
 
 			if (top_module_name.empty())
@@ -132,7 +132,7 @@ struct EdifBackend : public Backend {
 			for (auto cell_it : module->cells)
 			{
 				RTLIL::Cell *cell = cell_it.second;
-				if (!design->modules.count(cell->type) || design->modules.at(cell->type)->attributes.count("\\placeholder")) {
+				if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) {
 					lib_cell_ports[cell->type];
 					for (auto p : cell->connections) {
 						if (p.second.width > 1)
@@ -200,7 +200,7 @@ struct EdifBackend : public Backend {
 		for (auto module_it : design->modules)
 		{
 			RTLIL::Module *module = module_it.second;
-			if ((module->attributes.count("\\placeholder") > 0) > 0)
+			if (module->get_bool_attribute("\\placeholder"))
 				continue;
 
 			SigMap sigmap(module);
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 513c17531..83db8908c 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -132,7 +132,7 @@ struct IntersynthBackend : public Backend {
 			RTLIL::Module *module = module_it.second;
 			SigMap sigmap(module);
 
-			if (module->attributes.count("\\placeholder") > 0)
+			if (module->get_bool_attribute("\\placeholder"))
 				continue;
 			if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
 				continue;
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 6932e1420..e6e4ab4b0 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -181,7 +181,7 @@ struct SpiceBackend : public Backend {
 		for (auto module_it : design->modules)
 		{
 			RTLIL::Module *module = module_it.second;
-			if ((module->attributes.count("\\placeholder") > 0) > 0)
+			if (module->get_bool_attribute("\\placeholder"))
 				continue;
 
 			if (module->processes.size() != 0)
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 0eee4af40..88a48b584 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -957,7 +957,7 @@ struct VerilogBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
-			if ((it->second->attributes.count("\\placeholder") > 0) != placeholders)
+			if (it->second->get_bool_attribute("\\placeholder") != placeholders)
 				continue;
 			if (selected && !design->selected_whole_module(it->first)) {
 				if (design->selected_module(it->first))
-- 
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