From 2335c59e5bdd40c16ced821a27de7df00016963a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Mar 2020 10:09:01 -0800 Subject: abc: add abc.debug scratchpad option --- passes/techmap/abc.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 581652a41..e6c189c3e 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1553,6 +1553,11 @@ struct AbcPass : public Pass { show_tempdir = design->scratchpad_get_bool("abc.showtmp", show_tempdir); markgroups = design->scratchpad_get_bool("abc.markgroups", markgroups); + if (design->scratchpad_get_bool("abc.debug")) { + cleanup = false; + show_tempdir = true; + } + size_t argidx, g_argidx; bool g_arg_from_cmd = false; char pwd [PATH_MAX]; -- cgit v1.2.3 From 91a7a74ac438ba5b030d90fcfafeb1db03757d91 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Mar 2020 10:20:30 -0800 Subject: abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling --- backends/aiger/xaiger.cc | 7 ++++--- passes/techmap/abc9_ops.cc | 13 +++++-------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 402f41597..7b6b851b3 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -174,11 +174,12 @@ struct XAigerWriter undriven_bits.insert(bit); unused_bits.insert(bit); - bool keep = wire->get_bool_attribute(ID::keep); - if (wire->port_input || keep) + bool scc = wire->attributes.count(ID(abc9_scc)); + if (wire->port_input || scc) input_bits.insert(bit); - if (wire->port_output || keep) { + bool keep = wire->get_bool_attribute(ID::keep); + if (wire->port_output || keep || scc) { if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index b0bd81698..27e9fd239 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -110,14 +110,13 @@ void mark_scc(RTLIL::Module *module) if (c.second.is_fully_const()) continue; if (cell->output(c.first)) { SigBit b = c.second.as_bit(); + // TODO: Don't be as heavy handed as to + // mark the entire wire as part of the scc Wire *w = b.wire; - w->set_bool_attribute(ID::keep); - w->attributes[ID(abc9_scc_id)] = id.as_int(); + w->set_bool_attribute(ID(abc9_scc)); } } } - - module->fixup_ports(); } void prep_dff(RTLIL::Module *module) @@ -967,10 +966,8 @@ void reintegrate(RTLIL::Module *module) RTLIL::Wire *mapped_wire = mapped_mod->wire(port); RTLIL::Wire *wire = module->wire(port); log_assert(wire); - if (wire->attributes.erase(ID(abc9_scc_id))) { - auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep); - log_assert(r); - } + wire->attributes.erase(ID(abc9_scc)); + RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); -- cgit v1.2.3 From 80dcc8a0d1b6833f093c4ad6742c60187d1c9c00 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Mar 2020 10:30:07 -0800 Subject: abc9: for sccs, create a new wire instead of using entirety of existing --- passes/techmap/abc9_ops.cc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 27e9fd239..e1baf4e3d 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -93,9 +93,10 @@ void check(RTLIL::Design *design) void mark_scc(RTLIL::Module *module) { // For every unique SCC found, (arbitrarily) find the first - // cell in the component, and convert all wires driven by - // its output ports into a new PO, and drive its previous - // sinks with a new PI + // cell in the component, and replace its output connections + // with a new wire driven by the old connection but with a + // special (* abc9_scc *) attribute set (which is used by + // write_xaiger to break this wire into PI and POs) pool ids_seen; for (auto cell : module->cells()) { auto it = cell->attributes.find(ID(abc9_scc_id)); @@ -109,11 +110,10 @@ void mark_scc(RTLIL::Module *module) for (auto &c : cell->connections_) { if (c.second.is_fully_const()) continue; if (cell->output(c.first)) { - SigBit b = c.second.as_bit(); - // TODO: Don't be as heavy handed as to - // mark the entire wire as part of the scc - Wire *w = b.wire; + Wire *w = module->addWire(NEW_ID, GetSize(c.second)); w->set_bool_attribute(ID(abc9_scc)); + module->connect(w, c.second); + c.second = w; } } } -- cgit v1.2.3 From 3be7784d0e06f75d5e35eb356b726b559f647f13 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Mar 2020 10:51:47 -0800 Subject: xaiger: remove some unnecessary operations ... ... since they can not be triggered by (* keep *) anymore (but could still be triggered by (* abc9_scc *) !?!) --- backends/aiger/xaiger.cc | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7b6b851b3..cde6d066a 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -224,8 +224,6 @@ struct XAigerWriter alias_map[Q] = D; auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell)); log_assert(r.second); - if (input_bits.erase(Q)) - log_assert(Q.wire->attributes.count(ID::keep)); continue; } @@ -379,11 +377,6 @@ struct XAigerWriter alias_map[O] = b; ci_bits.emplace_back(b); undriven_bits.erase(O); - // If PI and CI, then must be a (* keep *) wire - if (input_bits.erase(O)) { - log_assert(output_bits.count(O)); - log_assert(O.wire->get_bool_attribute(ID::keep)); - } } } @@ -468,8 +461,8 @@ struct XAigerWriter for (const auto &bit : output_bits) { ordered_outputs[bit] = aig_o++; int aig; - // Unlike bit2aig() which checks aig_map first, for - // inout/keep bits, since aig_map will point to + // Unlike bit2aig() which checks aig_map first for + // inout/scc bits, since aig_map will point to // the PI, first attempt to find the NOT/AND driver // before resorting to an aig_map lookup (which // could be another PO) -- cgit v1.2.3