From d9a2b43014696fe07c96c822b1009503d052ffc4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Apr 2018 16:03:26 +0200 Subject: Add $dlatch support to write_verilog Signed-off-by: Clifford Wolf --- backends/verilog/verilog_backend.cc | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index bdf705056..b50dc12af 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -897,6 +897,42 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$dlatch") + { + RTLIL::SigSpec sig_en; + bool pol_en = false; + + sig_en = cell->getPort("\\EN"); + pol_en = cell->parameters["\\EN_POLARITY"].as_bool(); + + std::string reg_name = cellname(cell); + bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); + + if (!out_is_reg_wire) { + f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); + dump_reg_init(f, cell->getPort("\\Q")); + f << ";\n"; + } + + f << stringf("%s" "always @*\n", indent.c_str()); + + f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!"); + dump_sigspec(f, sig_en); + f << stringf(")\n"); + + f << stringf("%s" " %s = ", indent.c_str(), reg_name.c_str()); + dump_cell_expr_port(f, cell, "D", false); + f << stringf(";\n"); + + if (!out_is_reg_wire) { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Q")); + f << stringf(" = %s;\n", reg_name.c_str()); + } + + return true; + } + if (cell->type == "$mem") { RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string(); @@ -1537,6 +1573,8 @@ struct VerilogBackend : public Backend { reg_ct.insert("$dff"); reg_ct.insert("$adff"); + reg_ct.insert("$dffe"); + reg_ct.insert("$dlatch"); reg_ct.insert("$_DFF_N_"); reg_ct.insert("$_DFF_P_"); -- cgit v1.2.3