From 87910732f15c900cbd752158258a8af12720d277 Mon Sep 17 00:00:00 2001 From: diego Date: Thu, 16 Apr 2020 13:31:05 -0500 Subject: Adding tests for dynamic part select optimisation --- .../common/dynamic_part_select/forloop_select.v | 19 +++++++ .../common/dynamic_part_select/multiple_blocking.v | 19 +++++++ .../arch/common/dynamic_part_select/nonblocking.v | 14 +++++ tests/arch/common/dynamic_part_select/original.v | 13 +++++ tests/arch/common/dynamic_part_select/reset_test.v | 24 +++++++++ tests/arch/common/dynamic_part_select/reversed.v | 13 +++++ tests/arch/xilinx/dynamic_part_select.ys | 59 ++++++++++++++++++++++ 7 files changed, 161 insertions(+) create mode 100644 tests/arch/common/dynamic_part_select/forloop_select.v create mode 100644 tests/arch/common/dynamic_part_select/multiple_blocking.v create mode 100644 tests/arch/common/dynamic_part_select/nonblocking.v create mode 100644 tests/arch/common/dynamic_part_select/original.v create mode 100644 tests/arch/common/dynamic_part_select/reset_test.v create mode 100644 tests/arch/common/dynamic_part_select/reversed.v create mode 100644 tests/arch/xilinx/dynamic_part_select.ys diff --git a/tests/arch/common/dynamic_part_select/forloop_select.v b/tests/arch/common/dynamic_part_select/forloop_select.v new file mode 100644 index 000000000..9276a3ed8 --- /dev/null +++ b/tests/arch/common/dynamic_part_select/forloop_select.v @@ -0,0 +1,19 @@ +module forloop_select #(parameter WIDTH=256, SELW=4) + (input clk , + input [9:0] ctrl , + input [15:0] din , + input en, + output reg [WIDTH-1:0] dout); + + reg [SELW-1:0] sel; + localparam SLICE = WIDTH/(SELW**2); + + always @(posedge clk) + begin + if (en) begin + for (sel = 0; sel < 4'hf; sel=sel+1'b1) + dout[(ctrl*sel)+:SLICE] <= din; + end + end +endmodule + diff --git a/tests/arch/common/dynamic_part_select/multiple_blocking.v b/tests/arch/common/dynamic_part_select/multiple_blocking.v new file mode 100644 index 000000000..7861722d4 --- /dev/null +++ b/tests/arch/common/dynamic_part_select/multiple_blocking.v @@ -0,0 +1,19 @@ +module multiple_blocking #(parameter WIDTH=256, SELW=2) + (input clk , + input [9:0] ctrl , + input [15:0] din , + input [SELW-1:0] sel , + output reg [WIDTH:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + reg [9:0] a; + reg [SELW-1:0] b; + reg [15:0] c; + always @(posedge clk) begin + a = ctrl + 1; + b = sel - 1; + c = ~din; + dout = dout + 1; + dout[a*b+:SLICE] = c; + end +endmodule diff --git a/tests/arch/common/dynamic_part_select/nonblocking.v b/tests/arch/common/dynamic_part_select/nonblocking.v new file mode 100644 index 000000000..89c399522 --- /dev/null +++ b/tests/arch/common/dynamic_part_select/nonblocking.v @@ -0,0 +1,14 @@ +module nonblocking #(parameter WIDTH=256, SELW=2) + (input clk , + input [9:0] ctrl , + input [15:0] din , + input [SELW-1:0] sel , + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) begin + dout <= dout + 1; + dout[ctrl*sel+:SLICE] <= din ; + end + +endmodule diff --git a/tests/arch/common/dynamic_part_select/original.v b/tests/arch/common/dynamic_part_select/original.v new file mode 100644 index 000000000..bd7654ef5 --- /dev/null +++ b/tests/arch/common/dynamic_part_select/original.v @@ -0,0 +1,13 @@ +module original #(parameter WIDTH=256, SELW=2) + (input clk , + input [9:0] ctrl , + input [15:0] din , + input [SELW-1:0] sel , + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) + begin + dout[ctrl*sel+:SLICE] <= din ; + end +endmodule diff --git a/tests/arch/common/dynamic_part_select/reset_test.v b/tests/arch/common/dynamic_part_select/reset_test.v new file mode 100644 index 000000000..5a3a9b9fc --- /dev/null +++ b/tests/arch/common/dynamic_part_select/reset_test.v @@ -0,0 +1,24 @@ +module reset_test #(parameter WIDTH=256, SELW=2) + (input clk , + input [9:0] ctrl , + input [15:0] din , + input [SELW-1:0] sel , + input wire reset, + output reg [WIDTH-1:0] dout); + + reg [5:0] i; + wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}}; + localparam SLICE = WIDTH/(SELW**2); + // Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for + // whatever reason. + always @(posedge clk) begin + if (reset) begin: reset_mask + for (i = 0; i < 16; i=i+1) begin + dout[i*rval+:SLICE] <= 32'hDEAD; + end + end + //else begin + dout[ctrl*sel+:SLICE] <= din; + //end + end +endmodule diff --git a/tests/arch/common/dynamic_part_select/reversed.v b/tests/arch/common/dynamic_part_select/reversed.v new file mode 100644 index 000000000..6ef0e10be --- /dev/null +++ b/tests/arch/common/dynamic_part_select/reversed.v @@ -0,0 +1,13 @@ +module reversed #(parameter WIDTH=256, SELW=2) + (input clk , + input [9:0] ctrl , + input [15:0] din , + input [SELW-1:0] sel , + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) begin + dout[(1024-ctrl*sel)-:SLICE] <= din; + end +endmodule + diff --git a/tests/arch/xilinx/dynamic_part_select.ys b/tests/arch/xilinx/dynamic_part_select.ys new file mode 100644 index 000000000..597229cc9 --- /dev/null +++ b/tests/arch/xilinx/dynamic_part_select.ys @@ -0,0 +1,59 @@ +#### Original testcase ### +read_verilog ../common/dynamic_part_select/original.v +hierarchy -top original +prep -flatten -top original +design -save gold + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter + +### Multiple blocking assingments ### +read_verilog ../common/dynamic_part_select/multiple_blocking.v +hierarchy -top multiple_blocking +prep -flatten -top multiple_blocking +design -save gold + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter + +### Non-blocking to the same output register ### +read_verilog ../common/dynamic_part_select/nonblocking.v +hierarchy -top nonblocking +prep -flatten -top nonblocking +design -save gold + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter + +### For-loop select, one dynamic input +read_verilog ../common/dynamic_part_select/forloop_select.v +hierarchy -top forloop_select +prep -flatten -top forloop_select +design -save gold + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -seq 5 -prove-skip 1 miter + +### Double loop (part-select, reset) ### +read_verilog ../common/dynamic_part_select/reset_test.v +hierarchy -top reset_test +prep -flatten -top reset_test +design -save gold + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter + +### Reversed part-select case ### +read_verilog ../common/dynamic_part_select/reversed.v +hierarchy -top reversed +prep -flatten -top reversed +design -save gold + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -seq 20 -prove-skip 1 miter -- cgit v1.2.3 From 50581d5a94730b33e2ca1b7f7371f502ef9263c6 Mon Sep 17 00:00:00 2001 From: diego Date: Fri, 17 Apr 2020 10:15:22 -0500 Subject: Wrong fixed value --- tests/arch/common/dynamic_part_select/reversed.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/arch/common/dynamic_part_select/reversed.v b/tests/arch/common/dynamic_part_select/reversed.v index 6ef0e10be..5b0a77c11 100644 --- a/tests/arch/common/dynamic_part_select/reversed.v +++ b/tests/arch/common/dynamic_part_select/reversed.v @@ -7,7 +7,7 @@ module reversed #(parameter WIDTH=256, SELW=2) localparam SLICE = WIDTH/(SELW**2); always @(posedge clk) begin - dout[(1024-ctrl*sel)-:SLICE] <= din; + dout[(WIDTH-ctrl*sel)-:SLICE] <= din; end endmodule -- cgit v1.2.3 From 22f440506b2b58edc27354d9ac8d474bb6185e63 Mon Sep 17 00:00:00 2001 From: diego Date: Mon, 20 Apr 2020 12:45:35 -0500 Subject: Modifications of tests as per Eddie's request --- .../common/dynamic_part_select/forloop_select.v | 19 - tests/arch/xilinx/dynamic_part_select.ys | 59 --- tests/various/dynamic_part_select.ys | 119 +++++ tests/various/dynamic_part_select/forloop_select.v | 19 + .../dynamic_part_select/forloop_select_gate.v | 559 +++++++++++++++++++++ .../dynamic_part_select/multiple_blocking.v | 19 + .../dynamic_part_select/multiple_blocking_gate.v | 83 +++ tests/various/dynamic_part_select/nonblocking.v | 14 + .../various/dynamic_part_select/nonblocking_gate.v | 77 +++ tests/various/dynamic_part_select/original.v | 12 + tests/various/dynamic_part_select/original_gate.v | 74 +++ tests/various/dynamic_part_select/reset_test.v | 23 + .../various/dynamic_part_select/reset_test_gate.v | 151 ++++++ tests/various/dynamic_part_select/reversed.v | 13 + tests/various/dynamic_part_select/reversed_gate.v | 74 +++ 15 files changed, 1237 insertions(+), 78 deletions(-) delete mode 100644 tests/arch/common/dynamic_part_select/forloop_select.v delete mode 100644 tests/arch/xilinx/dynamic_part_select.ys create mode 100644 tests/various/dynamic_part_select.ys create mode 100644 tests/various/dynamic_part_select/forloop_select.v create mode 100644 tests/various/dynamic_part_select/forloop_select_gate.v create mode 100644 tests/various/dynamic_part_select/multiple_blocking.v create mode 100644 tests/various/dynamic_part_select/multiple_blocking_gate.v create mode 100644 tests/various/dynamic_part_select/nonblocking.v create mode 100644 tests/various/dynamic_part_select/nonblocking_gate.v create mode 100644 tests/various/dynamic_part_select/original.v create mode 100644 tests/various/dynamic_part_select/original_gate.v create mode 100644 tests/various/dynamic_part_select/reset_test.v create mode 100644 tests/various/dynamic_part_select/reset_test_gate.v create mode 100644 tests/various/dynamic_part_select/reversed.v create mode 100644 tests/various/dynamic_part_select/reversed_gate.v diff --git a/tests/arch/common/dynamic_part_select/forloop_select.v b/tests/arch/common/dynamic_part_select/forloop_select.v deleted file mode 100644 index 9276a3ed8..000000000 --- a/tests/arch/common/dynamic_part_select/forloop_select.v +++ /dev/null @@ -1,19 +0,0 @@ -module forloop_select #(parameter WIDTH=256, SELW=4) - (input clk , - input [9:0] ctrl , - input [15:0] din , - input en, - output reg [WIDTH-1:0] dout); - - reg [SELW-1:0] sel; - localparam SLICE = WIDTH/(SELW**2); - - always @(posedge clk) - begin - if (en) begin - for (sel = 0; sel < 4'hf; sel=sel+1'b1) - dout[(ctrl*sel)+:SLICE] <= din; - end - end -endmodule - diff --git a/tests/arch/xilinx/dynamic_part_select.ys b/tests/arch/xilinx/dynamic_part_select.ys deleted file mode 100644 index 597229cc9..000000000 --- a/tests/arch/xilinx/dynamic_part_select.ys +++ /dev/null @@ -1,59 +0,0 @@ -#### Original testcase ### -read_verilog ../common/dynamic_part_select/original.v -hierarchy -top original -prep -flatten -top original -design -save gold - -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad -miter -equiv -make_assert -flatten gold gate miter -sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter - -### Multiple blocking assingments ### -read_verilog ../common/dynamic_part_select/multiple_blocking.v -hierarchy -top multiple_blocking -prep -flatten -top multiple_blocking -design -save gold - -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad -miter -equiv -make_assert -flatten gold gate miter -sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter - -### Non-blocking to the same output register ### -read_verilog ../common/dynamic_part_select/nonblocking.v -hierarchy -top nonblocking -prep -flatten -top nonblocking -design -save gold - -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad -miter -equiv -make_assert -flatten gold gate miter -sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter - -### For-loop select, one dynamic input -read_verilog ../common/dynamic_part_select/forloop_select.v -hierarchy -top forloop_select -prep -flatten -top forloop_select -design -save gold - -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad -miter -equiv -make_assert -flatten gold gate miter -sat -verify -prove-asserts -show-public -seq 5 -prove-skip 1 miter - -### Double loop (part-select, reset) ### -read_verilog ../common/dynamic_part_select/reset_test.v -hierarchy -top reset_test -prep -flatten -top reset_test -design -save gold - -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad -miter -equiv -make_assert -flatten gold gate miter -sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter - -### Reversed part-select case ### -read_verilog ../common/dynamic_part_select/reversed.v -hierarchy -top reversed -prep -flatten -top reversed -design -save gold - -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad -miter -equiv -make_assert -flatten gold gate miter -sat -verify -prove-asserts -show-public -seq 20 -prove-skip 1 miter diff --git a/tests/various/dynamic_part_select.ys b/tests/various/dynamic_part_select.ys new file mode 100644 index 000000000..24c389068 --- /dev/null +++ b/tests/various/dynamic_part_select.ys @@ -0,0 +1,119 @@ +### Original testcase ### +read_verilog ./dynamic_part_select/original.v +hierarchy -top original; proc; opt; +prep -flatten -top original +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/original_gate.v +hierarchy -top original_gate; proc; opt; +prep -flatten -top original_gate +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +hierarchy -top equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv + +### Multiple blocking assingments ### +read_verilog ./dynamic_part_select/multiple_blocking.v +hierarchy -top multiple_blocking; proc; opt; +prep -flatten -top multiple_blocking +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/multiple_blocking_gate.v +hierarchy -top multiple_blocking_gate; proc; opt; +prep -flatten -top multiple_blocking_gate +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +hierarchy -top equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv + +### Non-blocking to the same output register ### +read_verilog ./dynamic_part_select/nonblocking.v +hierarchy -top nonblocking; proc; opt; +prep -flatten -top nonblocking +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/nonblocking_gate.v +hierarchy -top nonblocking_gate; proc; opt; +prep -flatten -top nonblocking_gate +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +hierarchy -top equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv + +### For-loop select, one dynamic input +read_verilog ./dynamic_part_select/forloop_select.v +hierarchy -top forloop_select; proc; opt; +prep -flatten -top forloop_select +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/forloop_select_gate.v +hierarchy -top forloop_select_gate; proc; opt; +prep -flatten -top forloop_select_gate +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +hierarchy -top equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv + +#### Double loop (part-select, reset) ### +read_verilog ./dynamic_part_select/reset_test.v +hierarchy -top reset_test; proc; opt; +prep -flatten -top reset_test +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/reset_test_gate.v +hierarchy -top reset_test_gate; proc; opt; +prep -flatten -top reset_test_gate +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +hierarchy -top equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv + +### Reversed part-select case ### +read_verilog ./dynamic_part_select/reversed.v +hierarchy -top reversed; proc; opt; +prep -flatten -top reversed +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/reversed_gate.v +hierarchy -top reversed_gate; proc; opt; +prep -flatten -top reversed_gate +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +hierarchy -top equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv diff --git a/tests/various/dynamic_part_select/forloop_select.v b/tests/various/dynamic_part_select/forloop_select.v new file mode 100644 index 000000000..8260f3186 --- /dev/null +++ b/tests/various/dynamic_part_select/forloop_select.v @@ -0,0 +1,19 @@ +module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input en, + output reg [WIDTH-1:0] dout); + + reg [SELW:0] sel; + localparam SLICE = WIDTH/(SELW**2); + + always @(posedge clk) + begin + if (en) begin + for (sel = 0; sel <= 4'hf; sel=sel+1'b1) + dout[(ctrl*sel)+:SLICE] <= din; + end + end +endmodule + diff --git a/tests/various/dynamic_part_select/forloop_select_gate.v b/tests/various/dynamic_part_select/forloop_select_gate.v new file mode 100644 index 000000000..71ae88537 --- /dev/null +++ b/tests/various/dynamic_part_select/forloop_select_gate.v @@ -0,0 +1,559 @@ +module forloop_select_gate (clk, ctrl, din, en, dout); + input clk; + input [3:0] ctrl; + input [15:0] din; + input en; + output reg [15:0] dout; + reg [4:0] sel; + always @(posedge clk) + case (|(en)) + 1'b 1: + begin + case (({(ctrl)*(0)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00001)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00010)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00011)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00100)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00101)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00110)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 00111)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01000)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01001)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01010)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01011)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01100)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01101)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01110)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + case (({(ctrl)*(5'b 01111)})+(0)) + 0: + dout[0:0] <= din; + 1: + dout[1:1] <= din; + 2: + dout[2:2] <= din; + 3: + dout[3:3] <= din; + 4: + dout[4:4] <= din; + 5: + dout[5:5] <= din; + 6: + dout[6:6] <= din; + 7: + dout[7:7] <= din; + 8: + dout[8:8] <= din; + 9: + dout[9:9] <= din; + 10: + dout[10:10] <= din; + 11: + dout[11:11] <= din; + 12: + dout[12:12] <= din; + 13: + dout[13:13] <= din; + 14: + dout[14:14] <= din; + 15: + dout[15:15] <= din; + endcase + sel = 5'b 10000; + end + endcase + endmodule diff --git a/tests/various/dynamic_part_select/multiple_blocking.v b/tests/various/dynamic_part_select/multiple_blocking.v new file mode 100644 index 000000000..2858f7741 --- /dev/null +++ b/tests/various/dynamic_part_select/multiple_blocking.v @@ -0,0 +1,19 @@ +module multiple_blocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + reg [CTRLW:0] a; + reg [SELW-1:0] b; + reg [DINW:0] c; + always @(posedge clk) begin + a = ctrl + 1; + b = sel - 1; + c = ~din; + dout = dout + 1; + dout[a*b+:SLICE] = c; + end +endmodule diff --git a/tests/various/dynamic_part_select/multiple_blocking_gate.v b/tests/various/dynamic_part_select/multiple_blocking_gate.v new file mode 100644 index 000000000..073b559dc --- /dev/null +++ b/tests/various/dynamic_part_select/multiple_blocking_gate.v @@ -0,0 +1,83 @@ +module multiple_blocking_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [1:0] din; + input [0:0] sel; + output reg [31:0] dout; + reg [5:0] a; + reg [0:0] b; + reg [2:0] c; + always @(posedge clk) + begin + a = (ctrl)+(1); + b = (sel)-(1); + c = ~(din); + dout = (dout)+(1); + case (({(a)*(b)})+(0)) + 0: + dout[31:0] = c; + 1: + dout[31:1] = c; + 2: + dout[31:2] = c; + 3: + dout[31:3] = c; + 4: + dout[31:4] = c; + 5: + dout[31:5] = c; + 6: + dout[31:6] = c; + 7: + dout[31:7] = c; + 8: + dout[31:8] = c; + 9: + dout[31:9] = c; + 10: + dout[31:10] = c; + 11: + dout[31:11] = c; + 12: + dout[31:12] = c; + 13: + dout[31:13] = c; + 14: + dout[31:14] = c; + 15: + dout[31:15] = c; + 16: + dout[31:16] = c; + 17: + dout[31:17] = c; + 18: + dout[31:18] = c; + 19: + dout[31:19] = c; + 20: + dout[31:20] = c; + 21: + dout[31:21] = c; + 22: + dout[31:22] = c; + 23: + dout[31:23] = c; + 24: + dout[31:24] = c; + 25: + dout[31:25] = c; + 26: + dout[31:26] = c; + 27: + dout[31:27] = c; + 28: + dout[31:28] = c; + 29: + dout[31:29] = c; + 30: + dout[31:30] = c; + 31: + dout[31:31] = c; + endcase + end +endmodule diff --git a/tests/various/dynamic_part_select/nonblocking.v b/tests/various/dynamic_part_select/nonblocking.v new file mode 100644 index 000000000..0949b31a9 --- /dev/null +++ b/tests/various/dynamic_part_select/nonblocking.v @@ -0,0 +1,14 @@ +module nonblocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) begin + dout <= dout + 1; + dout[ctrl*sel+:SLICE] <= din ; + end + +endmodule diff --git a/tests/various/dynamic_part_select/nonblocking_gate.v b/tests/various/dynamic_part_select/nonblocking_gate.v new file mode 100644 index 000000000..ed1ee2776 --- /dev/null +++ b/tests/various/dynamic_part_select/nonblocking_gate.v @@ -0,0 +1,77 @@ +module nonblocking_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [1:0] din; + input [0:0] sel; + output reg [31:0] dout; + always @(posedge clk) + begin + dout <= (dout)+(1); + case (({(ctrl)*(sel)})+(0)) + 0: + dout[31:0] <= din; + 1: + dout[31:1] <= din; + 2: + dout[31:2] <= din; + 3: + dout[31:3] <= din; + 4: + dout[31:4] <= din; + 5: + dout[31:5] <= din; + 6: + dout[31:6] <= din; + 7: + dout[31:7] <= din; + 8: + dout[31:8] <= din; + 9: + dout[31:9] <= din; + 10: + dout[31:10] <= din; + 11: + dout[31:11] <= din; + 12: + dout[31:12] <= din; + 13: + dout[31:13] <= din; + 14: + dout[31:14] <= din; + 15: + dout[31:15] <= din; + 16: + dout[31:16] <= din; + 17: + dout[31:17] <= din; + 18: + dout[31:18] <= din; + 19: + dout[31:19] <= din; + 20: + dout[31:20] <= din; + 21: + dout[31:21] <= din; + 22: + dout[31:22] <= din; + 23: + dout[31:23] <= din; + 24: + dout[31:24] <= din; + 25: + dout[31:25] <= din; + 26: + dout[31:26] <= din; + 27: + dout[31:27] <= din; + 28: + dout[31:28] <= din; + 29: + dout[31:29] <= din; + 30: + dout[31:30] <= din; + 31: + dout[31:31] <= din; + endcase + end +endmodule diff --git a/tests/various/dynamic_part_select/original.v b/tests/various/dynamic_part_select/original.v new file mode 100644 index 000000000..f7dfed1a1 --- /dev/null +++ b/tests/various/dynamic_part_select/original.v @@ -0,0 +1,12 @@ +module original #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) + begin + dout[ctrl*sel+:SLICE] <= din ; + end +endmodule diff --git a/tests/various/dynamic_part_select/original_gate.v b/tests/various/dynamic_part_select/original_gate.v new file mode 100644 index 000000000..22093bf63 --- /dev/null +++ b/tests/various/dynamic_part_select/original_gate.v @@ -0,0 +1,74 @@ +module original_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [1:0] din; + input [0:0] sel; + output reg [31:0] dout; + always @(posedge clk) + case (({(ctrl)*(sel)})+(0)) + 0: + dout[31:0] <= din; + 1: + dout[31:1] <= din; + 2: + dout[31:2] <= din; + 3: + dout[31:3] <= din; + 4: + dout[31:4] <= din; + 5: + dout[31:5] <= din; + 6: + dout[31:6] <= din; + 7: + dout[31:7] <= din; + 8: + dout[31:8] <= din; + 9: + dout[31:9] <= din; + 10: + dout[31:10] <= din; + 11: + dout[31:11] <= din; + 12: + dout[31:12] <= din; + 13: + dout[31:13] <= din; + 14: + dout[31:14] <= din; + 15: + dout[31:15] <= din; + 16: + dout[31:16] <= din; + 17: + dout[31:17] <= din; + 18: + dout[31:18] <= din; + 19: + dout[31:19] <= din; + 20: + dout[31:20] <= din; + 21: + dout[31:21] <= din; + 22: + dout[31:22] <= din; + 23: + dout[31:23] <= din; + 24: + dout[31:24] <= din; + 25: + dout[31:25] <= din; + 26: + dout[31:26] <= din; + 27: + dout[31:27] <= din; + 28: + dout[31:28] <= din; + 29: + dout[31:29] <= din; + 30: + dout[31:30] <= din; + 31: + dout[31:31] <= din; + endcase +endmodule diff --git a/tests/various/dynamic_part_select/reset_test.v b/tests/various/dynamic_part_select/reset_test.v new file mode 100644 index 000000000..29355aafb --- /dev/null +++ b/tests/various/dynamic_part_select/reset_test.v @@ -0,0 +1,23 @@ +module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + reg [SELW:0] i; + wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}}; + localparam SLICE = WIDTH/(SELW**2); + // Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for + // whatever reason. + always @(posedge clk) begin + if (reset) begin: reset_mask + for (i = 0; i < {SELW{1'b1}}; i=i+1) begin + dout[i*rval+:SLICE] <= 32'hDEAD; + end + end + //else begin + dout[ctrl*sel+:SLICE] <= din; + //end + end +endmodule diff --git a/tests/various/dynamic_part_select/reset_test_gate.v b/tests/various/dynamic_part_select/reset_test_gate.v new file mode 100644 index 000000000..96dff4135 --- /dev/null +++ b/tests/various/dynamic_part_select/reset_test_gate.v @@ -0,0 +1,151 @@ +module reset_test_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [1:0] din; + input [0:0] sel; + output reg [31:0] dout; + reg [1:0] i; + wire [0:0] rval; + assign rval = {reset, 1'b0 }; + always @(posedge clk) + begin + case (|(reset)) + 1'b 1: + begin + case (({(0)*(rval)})+(0)) + 0: + dout[31:0] <= 57005; + 1: + dout[31:1] <= 57005; + 2: + dout[31:2] <= 57005; + 3: + dout[31:3] <= 57005; + 4: + dout[31:4] <= 57005; + 5: + dout[31:5] <= 57005; + 6: + dout[31:6] <= 57005; + 7: + dout[31:7] <= 57005; + 8: + dout[31:8] <= 57005; + 9: + dout[31:9] <= 57005; + 10: + dout[31:10] <= 57005; + 11: + dout[31:11] <= 57005; + 12: + dout[31:12] <= 57005; + 13: + dout[31:13] <= 57005; + 14: + dout[31:14] <= 57005; + 15: + dout[31:15] <= 57005; + 16: + dout[31:16] <= 57005; + 17: + dout[31:17] <= 57005; + 18: + dout[31:18] <= 57005; + 19: + dout[31:19] <= 57005; + 20: + dout[31:20] <= 57005; + 21: + dout[31:21] <= 57005; + 22: + dout[31:22] <= 57005; + 23: + dout[31:23] <= 57005; + 24: + dout[31:24] <= 57005; + 25: + dout[31:25] <= 57005; + 26: + dout[31:26] <= 57005; + 27: + dout[31:27] <= 57005; + 28: + dout[31:28] <= 57005; + 29: + dout[31:29] <= 57005; + 30: + dout[31:30] <= 57005; + 31: + dout[31:31] <= 57005; + endcase + i = 1; + end + endcase + case (({(ctrl)*(sel)})+(0)) + 0: + dout[31:0] <= din; + 1: + dout[31:1] <= din; + 2: + dout[31:2] <= din; + 3: + dout[31:3] <= din; + 4: + dout[31:4] <= din; + 5: + dout[31:5] <= din; + 6: + dout[31:6] <= din; + 7: + dout[31:7] <= din; + 8: + dout[31:8] <= din; + 9: + dout[31:9] <= din; + 10: + dout[31:10] <= din; + 11: + dout[31:11] <= din; + 12: + dout[31:12] <= din; + 13: + dout[31:13] <= din; + 14: + dout[31:14] <= din; + 15: + dout[31:15] <= din; + 16: + dout[31:16] <= din; + 17: + dout[31:17] <= din; + 18: + dout[31:18] <= din; + 19: + dout[31:19] <= din; + 20: + dout[31:20] <= din; + 21: + dout[31:21] <= din; + 22: + dout[31:22] <= din; + 23: + dout[31:23] <= din; + 24: + dout[31:24] <= din; + 25: + dout[31:25] <= din; + 26: + dout[31:26] <= din; + 27: + dout[31:27] <= din; + 28: + dout[31:28] <= din; + 29: + dout[31:29] <= din; + 30: + dout[31:30] <= din; + 31: + dout[31:31] <= din; + endcase + end +endmodule diff --git a/tests/various/dynamic_part_select/reversed.v b/tests/various/dynamic_part_select/reversed.v new file mode 100644 index 000000000..8b114ac77 --- /dev/null +++ b/tests/various/dynamic_part_select/reversed.v @@ -0,0 +1,13 @@ +module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + localparam SLICE = WIDTH/(SELW**2); + always @(posedge clk) begin + dout[(WIDTH-ctrl*sel)-:SLICE] <= din; + end +endmodule + diff --git a/tests/various/dynamic_part_select/reversed_gate.v b/tests/various/dynamic_part_select/reversed_gate.v new file mode 100644 index 000000000..9349d45ee --- /dev/null +++ b/tests/various/dynamic_part_select/reversed_gate.v @@ -0,0 +1,74 @@ +module reversed_gate (clk, ctrl, din, sel, dout); + input clk; + input [4:0] ctrl; + input [15:0] din; + input [3:0] sel; + output reg [31:0] dout; + always @(posedge clk) + case ((({(32)-((ctrl)*(sel))})+(1))-(2)) + 0: + dout[1:0] <= din; + 1: + dout[2:1] <= din; + 2: + dout[3:2] <= din; + 3: + dout[4:3] <= din; + 4: + dout[5:4] <= din; + 5: + dout[6:5] <= din; + 6: + dout[7:6] <= din; + 7: + dout[8:7] <= din; + 8: + dout[9:8] <= din; + 9: + dout[10:9] <= din; + 10: + dout[11:10] <= din; + 11: + dout[12:11] <= din; + 12: + dout[13:12] <= din; + 13: + dout[14:13] <= din; + 14: + dout[15:14] <= din; + 15: + dout[16:15] <= din; + 16: + dout[17:16] <= din; + 17: + dout[18:17] <= din; + 18: + dout[19:18] <= din; + 19: + dout[20:19] <= din; + 20: + dout[21:20] <= din; + 21: + dout[22:21] <= din; + 22: + dout[23:22] <= din; + 23: + dout[24:23] <= din; + 24: + dout[25:24] <= din; + 25: + dout[26:25] <= din; + 26: + dout[27:26] <= din; + 27: + dout[28:27] <= din; + 28: + dout[29:28] <= din; + 29: + dout[30:29] <= din; + 30: + dout[31:30] <= din; + 31: + dout[31:31] <= din; + endcase +endmodule -- cgit v1.2.3 From 99a0958601def365caf980fc97ed77832ad7cbda Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 20 Apr 2020 11:53:48 -0700 Subject: Remove ununsed files --- .../common/dynamic_part_select/multiple_blocking.v | 19 ----------------- .../arch/common/dynamic_part_select/nonblocking.v | 14 ------------- tests/arch/common/dynamic_part_select/original.v | 13 ------------ tests/arch/common/dynamic_part_select/reset_test.v | 24 ---------------------- tests/arch/common/dynamic_part_select/reversed.v | 13 ------------ 5 files changed, 83 deletions(-) delete mode 100644 tests/arch/common/dynamic_part_select/multiple_blocking.v delete mode 100644 tests/arch/common/dynamic_part_select/nonblocking.v delete mode 100644 tests/arch/common/dynamic_part_select/original.v delete mode 100644 tests/arch/common/dynamic_part_select/reset_test.v delete mode 100644 tests/arch/common/dynamic_part_select/reversed.v diff --git a/tests/arch/common/dynamic_part_select/multiple_blocking.v b/tests/arch/common/dynamic_part_select/multiple_blocking.v deleted file mode 100644 index 7861722d4..000000000 --- a/tests/arch/common/dynamic_part_select/multiple_blocking.v +++ /dev/null @@ -1,19 +0,0 @@ -module multiple_blocking #(parameter WIDTH=256, SELW=2) - (input clk , - input [9:0] ctrl , - input [15:0] din , - input [SELW-1:0] sel , - output reg [WIDTH:0] dout); - - localparam SLICE = WIDTH/(SELW**2); - reg [9:0] a; - reg [SELW-1:0] b; - reg [15:0] c; - always @(posedge clk) begin - a = ctrl + 1; - b = sel - 1; - c = ~din; - dout = dout + 1; - dout[a*b+:SLICE] = c; - end -endmodule diff --git a/tests/arch/common/dynamic_part_select/nonblocking.v b/tests/arch/common/dynamic_part_select/nonblocking.v deleted file mode 100644 index 89c399522..000000000 --- a/tests/arch/common/dynamic_part_select/nonblocking.v +++ /dev/null @@ -1,14 +0,0 @@ -module nonblocking #(parameter WIDTH=256, SELW=2) - (input clk , - input [9:0] ctrl , - input [15:0] din , - input [SELW-1:0] sel , - output reg [WIDTH-1:0] dout); - - localparam SLICE = WIDTH/(SELW**2); - always @(posedge clk) begin - dout <= dout + 1; - dout[ctrl*sel+:SLICE] <= din ; - end - -endmodule diff --git a/tests/arch/common/dynamic_part_select/original.v b/tests/arch/common/dynamic_part_select/original.v deleted file mode 100644 index bd7654ef5..000000000 --- a/tests/arch/common/dynamic_part_select/original.v +++ /dev/null @@ -1,13 +0,0 @@ -module original #(parameter WIDTH=256, SELW=2) - (input clk , - input [9:0] ctrl , - input [15:0] din , - input [SELW-1:0] sel , - output reg [WIDTH-1:0] dout); - - localparam SLICE = WIDTH/(SELW**2); - always @(posedge clk) - begin - dout[ctrl*sel+:SLICE] <= din ; - end -endmodule diff --git a/tests/arch/common/dynamic_part_select/reset_test.v b/tests/arch/common/dynamic_part_select/reset_test.v deleted file mode 100644 index 5a3a9b9fc..000000000 --- a/tests/arch/common/dynamic_part_select/reset_test.v +++ /dev/null @@ -1,24 +0,0 @@ -module reset_test #(parameter WIDTH=256, SELW=2) - (input clk , - input [9:0] ctrl , - input [15:0] din , - input [SELW-1:0] sel , - input wire reset, - output reg [WIDTH-1:0] dout); - - reg [5:0] i; - wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}}; - localparam SLICE = WIDTH/(SELW**2); - // Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for - // whatever reason. - always @(posedge clk) begin - if (reset) begin: reset_mask - for (i = 0; i < 16; i=i+1) begin - dout[i*rval+:SLICE] <= 32'hDEAD; - end - end - //else begin - dout[ctrl*sel+:SLICE] <= din; - //end - end -endmodule diff --git a/tests/arch/common/dynamic_part_select/reversed.v b/tests/arch/common/dynamic_part_select/reversed.v deleted file mode 100644 index 5b0a77c11..000000000 --- a/tests/arch/common/dynamic_part_select/reversed.v +++ /dev/null @@ -1,13 +0,0 @@ -module reversed #(parameter WIDTH=256, SELW=2) - (input clk , - input [9:0] ctrl , - input [15:0] din , - input [SELW-1:0] sel , - output reg [WIDTH-1:0] dout); - - localparam SLICE = WIDTH/(SELW**2); - always @(posedge clk) begin - dout[(WIDTH-ctrl*sel)-:SLICE] <= din; - end -endmodule - -- cgit v1.2.3 From a1573058e989a807885b1df1e249b9b82c9cbef6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 20 Apr 2020 11:54:10 -0700 Subject: Simplify test case script --- tests/various/dynamic_part_select.ys | 47 +++++++++++++----------------------- 1 file changed, 17 insertions(+), 30 deletions(-) diff --git a/tests/various/dynamic_part_select.ys b/tests/various/dynamic_part_select.ys index 24c389068..d7fa14173 100644 --- a/tests/various/dynamic_part_select.ys +++ b/tests/various/dynamic_part_select.ys @@ -1,13 +1,11 @@ ### Original testcase ### read_verilog ./dynamic_part_select/original.v -hierarchy -top original; proc; opt; -prep -flatten -top original +proc rename -top gold design -stash gold read_verilog ./dynamic_part_select/original_gate.v -hierarchy -top original_gate; proc; opt; -prep -flatten -top original_gate +proc rename -top gate design -stash gate @@ -15,19 +13,17 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -hierarchy -top equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv ### Multiple blocking assingments ### +design -reset read_verilog ./dynamic_part_select/multiple_blocking.v -hierarchy -top multiple_blocking; proc; opt; -prep -flatten -top multiple_blocking +proc rename -top gold design -stash gold read_verilog ./dynamic_part_select/multiple_blocking_gate.v -hierarchy -top multiple_blocking_gate; proc; opt; -prep -flatten -top multiple_blocking_gate +proc rename -top gate design -stash gate @@ -35,19 +31,17 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -hierarchy -top equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv ### Non-blocking to the same output register ### +design -reset read_verilog ./dynamic_part_select/nonblocking.v -hierarchy -top nonblocking; proc; opt; -prep -flatten -top nonblocking +proc rename -top gold design -stash gold read_verilog ./dynamic_part_select/nonblocking_gate.v -hierarchy -top nonblocking_gate; proc; opt; -prep -flatten -top nonblocking_gate +proc rename -top gate design -stash gate @@ -55,19 +49,17 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -hierarchy -top equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv ### For-loop select, one dynamic input +design -reset read_verilog ./dynamic_part_select/forloop_select.v -hierarchy -top forloop_select; proc; opt; -prep -flatten -top forloop_select +proc rename -top gold design -stash gold read_verilog ./dynamic_part_select/forloop_select_gate.v -hierarchy -top forloop_select_gate; proc; opt; -prep -flatten -top forloop_select_gate +proc rename -top gate design -stash gate @@ -75,19 +67,17 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -hierarchy -top equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv #### Double loop (part-select, reset) ### +design -reset read_verilog ./dynamic_part_select/reset_test.v -hierarchy -top reset_test; proc; opt; -prep -flatten -top reset_test +proc rename -top gold design -stash gold read_verilog ./dynamic_part_select/reset_test_gate.v -hierarchy -top reset_test_gate; proc; opt; -prep -flatten -top reset_test_gate +proc rename -top gate design -stash gate @@ -95,19 +85,17 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -hierarchy -top equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv ### Reversed part-select case ### +design -reset read_verilog ./dynamic_part_select/reversed.v -hierarchy -top reversed; proc; opt; -prep -flatten -top reversed +proc rename -top gold design -stash gold read_verilog ./dynamic_part_select/reversed_gate.v -hierarchy -top reversed_gate; proc; opt; -prep -flatten -top reversed_gate +proc rename -top gate design -stash gate @@ -115,5 +103,4 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -hierarchy -top equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv -- cgit v1.2.3 From caf4071c8bd4494d2c86d3ef9ea7b17fc74bafca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 20 Apr 2020 11:58:23 -0700 Subject: Remove '-ignore_unknown_cells' option from 'sat' --- tests/various/dynamic_part_select.ys | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/various/dynamic_part_select.ys b/tests/various/dynamic_part_select.ys index d7fa14173..abc1daad6 100644 --- a/tests/various/dynamic_part_select.ys +++ b/tests/various/dynamic_part_select.ys @@ -13,7 +13,7 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv ### Multiple blocking assingments ### design -reset @@ -31,7 +31,7 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv ### Non-blocking to the same output register ### design -reset @@ -49,7 +49,7 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv ### For-loop select, one dynamic input design -reset @@ -67,7 +67,7 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv #### Double loop (part-select, reset) ### design -reset @@ -85,7 +85,7 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv ### Reversed part-select case ### design -reset @@ -103,4 +103,4 @@ design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv -sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv -- cgit v1.2.3