From c7a2e582aac966034d59def611bd53109ecb581e Mon Sep 17 00:00:00 2001
From: Ahmed Irfan <irfan@ubuntu.(none)>
Date: Thu, 16 Jan 2014 20:16:01 +0100
Subject: slice error corrected
---
backends/btor/btor.cc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index fcb6a47aa..6ef9c3fc1 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -172,9 +172,10 @@ struct BtorDumper
else
{
int prev_wire_line=0; //previously dumped wire line
- int start_bit=cell_output->width;
+ int start_bit=0;
for(unsigned j=0; j<cell_output->chunks.size(); ++j)
{
+ start_bit+=cell_output->chunks[j].width;
if(cell_output->chunks[j].wire->name == wire->name)
{
prev_wire_line = wire_line;
@@ -186,12 +187,11 @@ struct BtorDumper
if(prev_wire_line!=0)
{
++line_num;
- str = stringf("%d concat %d %d %d", line_num, wire_width, prev_wire_line, wire_line);
+ str = stringf("%d concat %d %d %d", line_num, wire_width, wire_line, prev_wire_line);
fprintf(f, "%s\n", str.c_str());
wire_line = line_num;
}
}
- start_bit-=cell_output->chunks[j].width;
}
}
}
@@ -531,7 +531,7 @@ struct BtorDumper
bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q"));
int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width);
- unsigned start_bit = output_width;
+ unsigned start_bit = 0;
for(unsigned i=0; i<cell_output->chunks.size(); ++i)
{
output_width = cell_output->chunks[i].width;
@@ -540,11 +540,11 @@ struct BtorDumper
int slice = value;
if(cell_output->chunks.size()>1)
{
+ start_bit+=output_width;
slice = ++line_num;
str = stringf ("%d slice %d %d %d %d;", line_num, output_width, value, start_bit-1,
start_bit-output_width);
fprintf(f, "%s\n", str.c_str());
- start_bit-=output_width;
}
if(cell->type == "$dffsr")
{
--
cgit v1.2.3