From dae7c593586f7a0bfc17d57e7d7fd96b2f6e167d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 8 Aug 2019 10:05:28 -0700
Subject: Add a few comments to document $alu and $lcu
---
techlibs/common/simlib.v | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a424d3089..5c6c52cf2 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -532,14 +532,15 @@ endmodule
// --------------------------------------------------------
-module \$lcu (P, G, CI, CO);
+module \$lcu (P, G, CI, CO); // Lookahead carry unit
parameter WIDTH = 1;
-input [WIDTH-1:0] P, G;
-input CI;
+input [WIDTH-1:0] P; // Propagate
+input [WIDTH-1:0] G; // Generate
+input CI; // Carry-in
-output reg [WIDTH-1:0] CO;
+output reg [WIDTH-1:0] CO; // Carry-out
integer i;
always @* begin
@@ -563,12 +564,14 @@ parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] X, Y;
+input [A_WIDTH-1:0] A; // Input operand
+input [B_WIDTH-1:0] B; // Input operand
+output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion)
+output [Y_WIDTH-1:0] Y; // Sum
-input CI, BI;
-output [Y_WIDTH-1:0] CO;
+input CI; // Carry-in
+input BI; // Invert-B
+output [Y_WIDTH-1:0] CO; // Carry-out
wire [Y_WIDTH-1:0] AA, BB;
--
cgit v1.2.3
From 5aef998957c00f1d7e5991d0c1122f49751d7311 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 09:48:17 -0700
Subject: Add more comments
---
techlibs/common/simlib.v | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 5c6c52cf2..f16866e86 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -532,7 +532,12 @@ endmodule
// --------------------------------------------------------
-module \$lcu (P, G, CI, CO); // Lookahead carry unit
+// Lookahead carry unit
+// A building block dedicated to fast computation of carry-bits
+// used in binary arithmetic operations. By replacing the ripple
+// carry structure used in full-adder blocks, the more significant
+// bits of the sum can be expected to be computed more quickly.
+module \$lcu (P, G, CI, CO);
parameter WIDTH = 1;
@@ -556,6 +561,12 @@ endmodule
// --------------------------------------------------------
+// Arithmetic logic unit
+// A building block supporting both binary addition/subtraction
+// operations, and indirectly, comparison operations.
+// Typically created by the `alumacc` pass, which transforms
+// $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
+// cells into this $alu cell.
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
@@ -566,11 +577,13 @@ parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A; // Input operand
input [B_WIDTH-1:0] B; // Input operand
-output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion)
+output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,
+ // used in combination with
+ // reduction-AND for $eq/$ne ops)
output [Y_WIDTH-1:0] Y; // Sum
-input CI; // Carry-in
-input BI; // Invert-B
+input CI; // Carry-in (set for $sub)
+input BI; // Invert-B (set for $sub)
output [Y_WIDTH-1:0] CO; // Carry-out
wire [Y_WIDTH-1:0] AA, BB;
@@ -587,6 +600,7 @@ endgenerate
wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
assign X = AA ^ BB;
+// Full adder
assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
function get_carry;
--
cgit v1.2.3
From acfb672d34092d67b0b3ed6a6ab45e5aac8e2bc0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 09:50:47 -0700
Subject: A bit more on where $lcu comes from
---
techlibs/common/simlib.v | 2 ++
1 file changed, 2 insertions(+)
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f16866e86..1b172c112 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -537,6 +537,8 @@ endmodule
// used in binary arithmetic operations. By replacing the ripple
// carry structure used in full-adder blocks, the more significant
// bits of the sum can be expected to be computed more quickly.
+// Typically created during `techmap` of $alu cells
+// (see the "_90_alu" rule in +/techmap.v)
module \$lcu (P, G, CI, CO);
parameter WIDTH = 1;
--
cgit v1.2.3
From 041defc5a60f702c8f6089a91d7c8679c751014b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 12:33:39 -0700
Subject: Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
---
techlibs/common/simlib.v | 59 ++++++++++++++++++++++++++++--------------------
1 file changed, 34 insertions(+), 25 deletions(-)
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 1b172c112..7845a3fed 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -532,20 +532,24 @@ endmodule
// --------------------------------------------------------
-// Lookahead carry unit
-// A building block dedicated to fast computation of carry-bits
-// used in binary arithmetic operations. By replacing the ripple
-// carry structure used in full-adder blocks, the more significant
-// bits of the sum can be expected to be computed more quickly.
-// Typically created during `techmap` of $alu cells
-// (see the "_90_alu" rule in +/techmap.v)
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $lcu (P, G, CI, CO)
+//-
+//- Lookahead carry unit
+//- A building block dedicated to fast computation of carry-bits used in binary
+//- arithmetic operations. By replacing the ripple carry structure used in full-adder
+//- blocks, the more significant bits of the sum can be expected to be computed more
+//- quickly.
+//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
+//- +/techmap.v).
module \$lcu (P, G, CI, CO);
parameter WIDTH = 1;
-input [WIDTH-1:0] P; // Propagate
-input [WIDTH-1:0] G; // Generate
-input CI; // Carry-in
+input [WIDTH-1:0] P; // Propagate
+input [WIDTH-1:0] G; // Generate
+input CI; // Carry-in
output reg [WIDTH-1:0] CO; // Carry-out
@@ -563,12 +567,17 @@ endmodule
// --------------------------------------------------------
-// Arithmetic logic unit
-// A building block supporting both binary addition/subtraction
-// operations, and indirectly, comparison operations.
-// Typically created by the `alumacc` pass, which transforms
-// $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
-// cells into this $alu cell.
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $alu (A, B, CI, BI, X, Y, CO)
+//-
+//- Arithmetic logic unit.
+//- A building block supporting both binary addition/subtraction operations, and
+//- indirectly, comparison operations.
+//- Typically created by the `alumacc` pass, which transforms:
+//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
+//- cells into this $alu cell.
+//-
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
@@ -577,16 +586,16 @@ parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
-input [A_WIDTH-1:0] A; // Input operand
-input [B_WIDTH-1:0] B; // Input operand
-output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,
- // used in combination with
- // reduction-AND for $eq/$ne ops)
-output [Y_WIDTH-1:0] Y; // Sum
+input [A_WIDTH-1:0] A; // Input operand
+input [B_WIDTH-1:0] B; // Input operand
+output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,
+ // used in combination with
+ // reduction-AND for $eq/$ne ops)
+output [Y_WIDTH-1:0] Y; // Sum
-input CI; // Carry-in (set for $sub)
-input BI; // Invert-B (set for $sub)
-output [Y_WIDTH-1:0] CO; // Carry-out
+input CI; // Carry-in (set for $sub)
+input BI; // Invert-B (set for $sub)
+output [Y_WIDTH-1:0] CO; // Carry-out
wire [Y_WIDTH-1:0] AA, BB;
--
cgit v1.2.3