From 9c61fb0e0c23f00bacf316f7efd358c66f2f6397 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 16:57:54 -0700
Subject: Add comment as per @cliffordwolf
---
passes/techmap/shregmap.cc | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 46f6a79fb..8881ba468 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -295,7 +295,18 @@ struct ShregmapWorker
{
auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
if (!r.second) {
+ // Insertion not successful means that d_bit is already
+ // connected to another register, thus mark it as a
+ // non chain user ...
sigbit_with_non_chain_users.insert(d_bit);
+ // ... and clone d_bit into another wire, and use that
+ // wire as a different key in the d_bit-to-cell dictionary
+ // so that it can be identified as another chain
+ // (omitting this common flop)
+ // Link: https://github.com/YosysHQ/yosys/pull/1085
+ // NB: This relies on us not updating sigmap with this
+ // alias otherwise it would think they are the same
+ // wire
Wire *wire = module->addWire(NEW_ID);
module->connect(wire, d_bit);
sigbit_chain_next.insert(std::make_pair(wire, cell));
--
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