From 96c7d60304e4e9e4cb4d85924efcafa546283c65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Tue, 25 May 2021 15:34:12 +0200 Subject: memory_bram: Respect write port priority. --- passes/memory/memory_bram.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index a860fc693..6ec3dc2e9 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -1071,6 +1071,20 @@ void handle_memory(Mem &mem, const rules_t &rules) } } + // This pass cannot deal with write port priority — we need to emulate it, + // if present. Since priority emulation will change the enable signals, + // which in turn may change enable grouping and mapping eligibility in + // pathological cases, we need to do this before checking mapping + // eligibility. This will create priority emulation logic for all + // memories in the design regardless of whether we end up mapping them + // or not, but since we never call Mem::emit(), the new priority masks + // and enables won't be commited to the design, and this logic will be + // unused (and removed by subsequent opt_clean) for unmapped memories. + + for (int i = 0; i < GetSize(mem.wr_ports); i++) + for (int j = 0; j < i; j++) + mem.emulate_priority(j, i); + pool> failed_brams; dict, tuple> best_rule_cache; -- cgit v1.2.3