From 9465b2af95a146f514fc1e0b2d31bc3d9a233fb7 Mon Sep 17 00:00:00 2001
From: KrystalDelusion <krystinedawn@yosyshq.com>
Date: Wed, 24 Aug 2022 10:28:27 +1200
Subject: Fitting help messages to 80 character width

Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
---
 backends/blif/blif.cc                   |  4 +-
 backends/edif/edif.cc                   |  4 +-
 backends/json/json.cc                   |  8 ++--
 backends/verilog/verilog_backend.cc     |  3 +-
 frontends/rpc/rpc_frontend.cc           | 12 +++---
 passes/cmds/bugpoint.cc                 |  8 ++--
 passes/cmds/chformal.cc                 |  4 +-
 passes/cmds/exec.cc                     |  4 +-
 passes/cmds/glift.cc                    | 76 +++++++++++++++++----------------
 passes/cmds/logcmd.cc                   |  5 ++-
 passes/cmds/scratchpad.cc               |  3 +-
 passes/cmds/select.cc                   |  2 +-
 passes/hierarchy/submod.cc              |  4 +-
 passes/memory/memory_bram.cc            |  3 +-
 passes/memory/memory_dff.cc             |  4 +-
 passes/memory/memory_share.cc           |  4 +-
 passes/opt/opt_dff.cc                   | 11 +++--
 passes/pmgen/xilinx_srl.cc              |  6 +--
 passes/sat/qbfsat.cc                    | 45 ++++++++++---------
 passes/sat/sim.cc                       |  7 +--
 passes/techmap/abc.cc                   |  7 +--
 passes/techmap/abc9.cc                  |  4 +-
 passes/techmap/abc9_exe.cc              |  4 +-
 passes/techmap/abc9_ops.cc              | 40 ++++++++---------
 passes/techmap/dfflegalize.cc           | 38 ++++++-----------
 passes/techmap/dfflibmap.cc             |  2 +-
 passes/techmap/dffunmap.cc              |  4 +-
 passes/techmap/simplemap.cc             |  3 +-
 passes/techmap/techmap.cc               | 18 ++++----
 techlibs/ice40/synth_ice40.cc           |  4 +-
 techlibs/intel/synth_intel.cc           | 13 +++---
 techlibs/intel_alm/synth_intel_alm.cc   | 13 +++---
 techlibs/quicklogic/synth_quicklogic.cc |  4 +-
 techlibs/sf2/synth_sf2.cc               |  4 +-
 techlibs/xilinx/synth_xilinx.cc         |  7 +--
 35 files changed, 198 insertions(+), 184 deletions(-)

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index ba29d9090..23d1d58fc 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -512,8 +512,8 @@ struct BlifBackend : public Backend {
 		log("        suppresses the generation of this nets without fanout.\n");
 		log("\n");
 		log("The following options can be useful when the generated file is not going to be\n");
-		log("read by a BLIF parser but a custom tool. It is recommended to not name the output\n");
-		log("file *.blif when any of this options is used.\n");
+		log("read by a BLIF parser but a custom tool. It is recommended to not name the\n");
+		log("output file *.blif when any of this options is used.\n");
 		log("\n");
 		log("    -icells\n");
 		log("        do not translate Yosys's internal gates to generic BLIF logic\n");
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 370108444..7722d0c33 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -107,8 +107,8 @@ struct EdifBackend : public Backend {
 		log("        constant drivers first)\n");
 		log("\n");
 		log("    -gndvccy\n");
-		log("        create \"GND\" and \"VCC\" cells with \"Y\" outputs. (the default is \"G\"\n");
-		log("        for \"GND\" and \"P\" for \"VCC\".)\n");
+		log("        create \"GND\" and \"VCC\" cells with \"Y\" outputs. (the default is\n");
+		log("        \"G\" for \"GND\" and \"P\" for \"VCC\".)\n");
 		log("\n");
 		log("    -attrprop\n");
 		log("        create EDIF properties for cell attributes\n");
diff --git a/backends/json/json.cc b/backends/json/json.cc
index 270d762ee..1ff0a6c66 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -397,8 +397,8 @@ struct JsonBackend : public Backend {
 		log("      \"signed\": <1 if the port is signed>\n");
 		log("    }\n");
 		log("\n");
-		log("The \"offset\" and \"upto\" fields are skipped if their value would be 0.");
-		log("They don't affect connection semantics, and are only used to preserve original");
+		log("The \"offset\" and \"upto\" fields are skipped if their value would be 0.\n");
+		log("They don't affect connection semantics, and are only used to preserve original\n");
 		log("HDL bit indexing.");
 		log("And <cell_details> is:\n");
 		log("\n");
@@ -459,8 +459,8 @@ struct JsonBackend : public Backend {
 		log("connected to a constant driver are denoted as string \"0\", \"1\", \"x\", or\n");
 		log("\"z\" instead of a number.\n");
 		log("\n");
-		log("Bit vectors (including integers) are written as string holding the binary");
-		log("representation of the value. Strings are written as strings, with an appended");
+		log("Bit vectors (including integers) are written as string holding the binary\n");
+		log("representation of the value. Strings are written as strings, with an appended\n");
 		log("blank in cases of strings of the form /[01xz]* */.\n");
 		log("\n");
 		log("For example the following Verilog code:\n");
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index aa1d4558c..e60ebc70e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2160,7 +2160,8 @@ struct VerilogBackend : public Backend {
 		log("        as binary numbers.\n");
 		log("\n");
 		log("    -simple-lhs\n");
-		log("        Connection assignments with simple left hand side without concatenations.\n");
+		log("        Connection assignments with simple left hand side without\n");
+		log("        concatenations.\n");
 		log("\n");
 		log("    -extmem\n");
 		log("        instead of initializing memories using assignments to individual\n");
diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc
index c12640ef0..ec3952661 100644
--- a/frontends/rpc/rpc_frontend.cc
+++ b/frontends/rpc/rpc_frontend.cc
@@ -383,12 +383,12 @@ struct RpcFrontend : public Pass {
 		log("        request for the module <module-name> to be derived for a specific set of\n");
 		log("        parameters. <param-name> starts with \\ for named parameters, and with $\n");
 		log("        for unnamed parameters, which are numbered starting at 1.<param-value>\n");
-		log("        for integer parameters is always specified as a binary string of unlimited\n");
-		log("        precision. the <source> returned by the frontend is hygienically parsed\n");
-		log("        by a built-in Yosys <frontend>, allowing the RPC frontend to return any\n");
-		log("        convenient representation of the module. the derived module is cached,\n");
-		log("        so the response should be the same whenever the same set of parameters\n");
-		log("        is provided.\n");
+		log("        for integer parameters is always specified as a binary string of\n");
+		log("        unlimited precision. the <source> returned by the frontend is\n");
+		log("        hygienically parsedby a built-in Yosys <frontend>, allowing the RPC\n");
+		log("        frontend to return anyconvenient representation of the module. the\n");
+		log("        derived module is cached,so the response should be the same whenever the\n");
+		log("        same set of parameters is provided.\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index 7b621504d..e666023fa 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -34,10 +34,10 @@ struct BugpointPass : public Pass {
 		log("\n");
 		log("This command minimizes the current design that is known to crash Yosys with the\n");
 		log("given script into a smaller testcase. It does this by removing an arbitrary part\n");
-		log("of the design and recursively invokes a new Yosys process with this modified design\n");
-		log("and the same script, repeating these steps while it can find a smaller design that\n");
-		log("still causes a crash. Once this command finishes, it replaces the current design\n");
-		log("with the smallest testcase it was able to produce.\n");
+		log("of the design and recursively invokes a new Yosys process with this modified\n");
+		log("design and the same script, repeating these steps while it can find a smaller\n");
+		log("design that still causes a crash. Once this command finishes, it replaces the\n");
+		log("current design with the smallest testcase it was able to produce.\n");
 		log("In order to save the reduced testcase you must write this out to a file with\n");
 		log("another command after `bugpoint` like `write_rtlil` or `write_verilog`.\n");
 		log("\n");
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc
index d813a449c..66044b161 100644
--- a/passes/cmds/chformal.cc
+++ b/passes/cmds/chformal.cc
@@ -32,8 +32,8 @@ struct ChformalPass : public Pass {
 		log("    chformal [types] [mode] [options] [selection]\n");
 		log("\n");
 		log("Make changes to the formal constraints of the design. The [types] options\n");
-		log("the type of constraint to operate on. If none of the following options are given,\n");
-		log("the command will operate on all constraint types:\n");
+		log("the type of constraint to operate on. If none of the following options are\n");
+		log("given, the command will operate on all constraint types:\n");
 		log("\n");
 		log("    -assert       $assert cells, representing assert(...) constraints\n");
 		log("    -assume       $assume cells, representing assume(...) constraints\n");
diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc
index f00629a02..c15ef23bf 100644
--- a/passes/cmds/exec.cc
+++ b/passes/cmds/exec.cc
@@ -46,8 +46,8 @@ struct ExecPass : public Pass {
 		log("\n");
 		log("Execute a command in the operating system shell.  All supplied arguments are\n");
 		log("concatenated and passed as a command to popen(3).  Whitespace is not guaranteed\n");
-		log("to be preserved, even if quoted.  stdin and stderr are not connected, while stdout is\n");
-		log("logged unless the \"-q\" option is specified.\n");
+		log("to be preserved, even if quoted.  stdin and stderr are not connected, while\n");
+		log("stdout is logged unless the \"-q\" option is specified.\n");
 		log("\n");
 		log("\n");
 		log("    -q\n");
diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc
index b398c3e04..439ded076 100644
--- a/passes/cmds/glift.cc
+++ b/passes/cmds/glift.cc
@@ -431,45 +431,46 @@ struct GliftPass : public Pass {
 		log("\n");
 		log("    glift <command> [options] [selection]\n");
 		log("\n");
-		log("Augments the current or specified module with gate-level information flow tracking\n");
-		log("(GLIFT) logic using the \"constructive mapping\" approach. Also can set up QBF-SAT\n");
-		log("optimization problems in order to optimize GLIFT models or trade off precision and\n");
-		log("complexity.\n");
+		log("Augments the current or specified module with gate-level information flow \n");
+		log("tracking (GLIFT) logic using the \"constructive mapping\" approach. Also can set\n");
+		log("up QBF-SAT optimization problems in order to optimize GLIFT models or trade off\n");
+		log("precision and complexity.\n");
 		log("\n");
 		log("\n");
 		log("Commands:\n");
 		log("\n");
 		log("  -create-precise-model\n");
-		log("    Replaces the current or specified module with one that has corresponding \"taint\"\n");
-		log("    inputs, outputs, and internal nets along with precise taint tracking logic.\n");
-		log("    For example, precise taint tracking logic for an AND gate is:\n");
+		log("    Replaces the current or specified module with one that has corresponding\n");
+		log("    \"taint\" inputs, outputs, and internal nets along with precise taint\n");
+		log("    tracking logic. For example, precise taint tracking logic for an AND gate\n");
+		log("    is:\n");
 		log("\n");
 		log("      y_t = a & b_t | b & a_t | a_t & b_t\n");
 		log("\n");
 		log("\n");
 		log("  -create-imprecise-model\n");
-		log("    Replaces the current or specified module with one that has corresponding \"taint\"\n");
-		log("    inputs, outputs, and internal nets along with imprecise \"All OR\" taint tracking\n");
-		log("    logic:\n");
+		log("    Replaces the current or specified module with one that has corresponding\n");
+		log("    \"taint\" inputs, outputs, and internal nets along with imprecise \"All OR\"\n");
+		log("    taint tracking logic:\n");
 		log("\n");
 		log("      y_t = a_t | b_t\n");
 		log("\n");
 		log("\n");
 		log("  -create-instrumented-model\n");
-		log("    Replaces the current or specified module with one that has corresponding \"taint\"\n");
-		log("    inputs, outputs, and internal nets along with 4 varying-precision versions of taint\n");
-		log("    tracking logic. Which version of taint tracking logic is used for a given gate is\n");
-		log("    determined by a MUX selected by an $anyconst cell.  By default, unless the\n");
-		log("    `-no-cost-model` option is provided, an additional wire named `__glift_weight` with\n");
-		log("    the `keep` and `minimize` attributes is added to the module along with pmuxes and\n");
-		log("    adders to calculate a rough estimate of the number of logic gates in the GLIFT model\n");
-		log("    given an assignment for the $anyconst cells. The four versions of taint tracking logic\n");
-		log("    for an AND gate are:");
-		log("\n");
-		log("      y_t = a & b_t | b & a_t | a_t & b_t           (like `-create-precise-model`)\n");
+		log("    Replaces the current or specified module with one that has corresponding\n");
+		log("    \"taint\" inputs, outputs, and internal nets along with 4 varying-precision\n");
+		log("    versions of taint tracking logic. Which version of taint tracking logic is\n");
+		log("    used for a given gate is determined by a MUX selected by an $anyconst cell.\n");
+		log("     By default, unless the `-no-cost-model` option is provided, an additional\n");
+		log("    wire named `__glift_weight` with the `keep` and `minimize` attributes is\n");
+		log("    added to the module along with pmuxes and adders to calculate a rough\n");
+		log("    estimate of the number of logic gates in the GLIFT model given an assignment\n");
+		log("    for the $anyconst cells. The four versions of taint tracking logic for an\n");
+		log("    AND gate are:\n");
+		log("      y_t = a & b_t | b & a_t | a_t & b_t       (like `-create-precise-model`)\n");
 		log("      y_t = a_t | a & b_t\n");
 		log("      y_t = b_t | b & a_t\n");
-		log("      y_t = a_t | b_t                               (like `-create-imprecise-model`)\n");
+		log("      y_t = a_t | b_t                           (like `-create-imprecise-model`)\n");
 		log("\n");
 		log("\n");
 		log("Options:\n");
@@ -479,27 +480,30 @@ struct GliftPass : public Pass {
 		log("    (default: label constants as un-tainted)\n");
 		log("\n");
 		log("  -keep-outputs\n");
-		log("    Do not remove module outputs. Taint tracking outputs will appear in the module ports\n");
-		log("    alongside the orignal outputs.\n");
+		log("    Do not remove module outputs. Taint tracking outputs will appear in the\n");
+		log("    module ports alongside the orignal outputs.\n");
 		log("    (default: original module outputs are removed)\n");
 		log("\n");
 		log("  -simple-cost-model\n");
-		log("    Do not model logic area. Instead model the number of non-zero assignments to $anyconsts.\n");
-		log("    Taint tracking logic versions vary in their size, but all reduced-precision versions are\n");
-		log("    significantly smaller than the fully-precise version. A non-zero $anyconst assignment means\n");
-		log("    that reduced-precision taint tracking logic was chosen for some gate.\n");
-		log("    Only applicable in combination with `-create-instrumented-model`.\n");
-		log("    (default: use a complex model and give that wire the \"keep\" and \"minimize\" attributes)\n");
+		log("    Do not model logic area. Instead model the number of non-zero assignments to\n");
+		log("    $anyconsts. Taint tracking logic versions vary in their size, but all\n");
+		log("    reduced-precision versions are significantly smaller than the fully-precise\n");
+		log("    version. A non-zero $anyconst assignment means that reduced-precision taint\n");
+		log("    tracking logic was chosen for some gate. Only applicable in combination with\n");
+		log("    `-create-instrumented-model`. (default: use a complex model and give that\n");
+		log("     wire the \"keep\" and \"minimize\" attributes)\n");
 		log("\n");
 		log("  -no-cost-model\n");
-		log("    Do not model taint tracking logic area and do not create a `__glift_weight` wire.\n");
-		log("    Only applicable in combination with `-create-instrumented-model`.\n");
-		log("    (default: model area and give that wire the \"keep\" and \"minimize\" attributes)\n");
+		log("    Do not model taint tracking logic area and do not create a `__glift_weight`\n");
+		log("    wire. Only applicable in combination with `-create-instrumented-model`.\n");
+		log("    (default: model area and give that wire the \"keep\" and \"minimize\"\n");
+		log("    attributes)\n");
 		log("\n");
 		log("  -instrument-more\n");
-		log("    Allow choice from more versions of (even simpler) taint tracking logic. A total\n");
-		log("    of 8 versions of taint tracking logic will be added per gate, including the 4\n");
-		log("    versions from `-create-instrumented-model` and these additional versions:\n");
+		log("    Allow choice from more versions of (even simpler) taint tracking logic. A\n");
+		log("    total of 8 versions of taint tracking logic will be added per gate,\n");
+		log("    including the 4 versions from `-create-instrumented-model` and these\n");
+		log("    additional versions:\n");
 		log("\n");
 		log("      y_t = a_t\n");
 		log("      y_t = b_t\n");
diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc
index f1702400d..20cbd8943 100644
--- a/passes/cmds/logcmd.cc
+++ b/passes/cmds/logcmd.cc
@@ -38,8 +38,9 @@ struct LogPass : public Pass {
 		log("logfiles.\n");
 		log("\n");
 		log("    -stdout\n");
-		log("        Print the output to stdout too. This is useful when all Yosys is executed\n");
-		log("        with a script and the -q (quiet operation) argument to notify the user.\n");
+		log("        Print the output to stdout too. This is useful when all Yosys is\n");
+		log("        executed with a script and the -q (quiet operation) argument to notify\n");
+		log("        the user.\n");
 		log("\n");
 		log("    -stderr\n");
 		log("        Print the output to stderr too.\n");
diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc
index 015eb97e7..aecc4c17d 100644
--- a/passes/cmds/scratchpad.cc
+++ b/passes/cmds/scratchpad.cc
@@ -49,7 +49,8 @@ struct ScratchpadPass : public Pass {
 		log("        copy the value of the first identifier to the second identifier.\n");
 		log("\n");
 		log("    -assert <identifier> <value>\n");
-		log("        assert that the entry for the given identifier is set to the given value.\n");
+		log("        assert that the entry for the given identifier is set to the given\n");
+		log("        value.\n");
 		log("\n");
 		log("    -assert-set <identifier>\n");
 		log("        assert that the entry for the given identifier exists.\n");
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index b112b145c..fdf56641c 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1125,7 +1125,7 @@ struct SelectPass : public Pass {
 		log("    <obj_pattern>\n");
 		log("        select the specified object(s) from the current module\n");
 		log("\n");
-		log("By default, patterns will not match black/white-box modules or their");
+		log("By default, patterns will not match black/white-box modules or their\n");
 		log("contents. To include such objects, prefix the pattern with '='.\n");
 		log("\n");
 		log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index c0c40671d..8476d392c 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -348,8 +348,8 @@ struct SubmodPass : public Pass {
 		log("\n");
 		log("    -hidden\n");
 		log("        instead of creating submodule ports with public names, create ports with\n");
-		log("        private names so that a subsequent 'flatten; clean' call will restore the\n");
-		log("        original module with original public names.\n");
+		log("        private names so that a subsequent 'flatten; clean' call will restore\n");
+		log("        the original module with original public names.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index b1f45d5fc..1cb50b3ea 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1245,7 +1245,8 @@ struct MemoryBramPass : public Pass {
 		log("greater than 1 share the same configuration bit.\n");
 		log("\n");
 		log("Using the same bram name in different bram blocks will create different variants\n");
-		log("of the bram. Verilog configuration parameters for the bram are created as needed.\n");
+		log("of the bram. Verilog configuration parameters for the bram are created as\n");
+		log("needed.\n");
 		log("\n");
 		log("It is also possible to create variants by repeating statements in the bram block\n");
 		log("and appending '@<label>' to the individual statements.\n");
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 998e86491..75c6e6a3a 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -631,8 +631,8 @@ struct MemoryDffPass : public Pass {
 		log("\n");
 		log("    memory_dff [-no-rw-check] [selection]\n");
 		log("\n");
-		log("This pass detects DFFs at memory read ports and merges them into the memory port.\n");
-		log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
+		log("This pass detects DFFs at memory read ports and merges them into the memory\n");
+		log("port. I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
 		log("interface and yields a synchronous memory port.\n");
 		log("\n");
 		log("    -no-rw-check\n");
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 5cb11d62b..8b2354ef8 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -523,8 +523,8 @@ struct MemorySharePass : public Pass {
 		log("  - When multiple write ports access the same address then this is converted\n");
 		log("    to a single write port with a more complex data and/or enable logic path.\n");
 		log("\n");
-		log("  - When multiple read or write ports access adjacent aligned addresses, they are\n");
-		log("    merged to a single wide read or write port.  This transformation can be\n");
+		log("  - When multiple read or write ports access adjacent aligned addresses, they\n");
+		log("    are merged to a single wide read or write port.  This transformation can be\n");
 		log("    disabled with the \"-nowiden\" option.\n");
 		log("\n");
 		log("  - When multiple write ports are never accessed at the same time (a SAT\n");
diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc
index 6ff2d1b4b..f090d20b2 100644
--- a/passes/opt/opt_dff.cc
+++ b/passes/opt/opt_dff.cc
@@ -853,14 +853,17 @@ struct OptDffPass : public Pass {
 		log("    opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] [selection]\n");
 		log("\n");
 		log("This pass converts flip-flops to a more suitable type by merging clock enables\n");
-		log("and synchronous reset multiplexers, removing unused control inputs, or potentially\n");
-		log("removes the flip-flop altogether, converting it to a constant driver.\n");
+		log("and synchronous reset multiplexers, removing unused control inputs, or\n");
+		log("potentially removes the flip-flop altogether, converting it to a constant\n");
+		log("driver.\n");
 		log("\n");
 		log("    -nodffe\n");
-		log("        disables dff -> dffe conversion, and other transforms recognizing clock enable\n");
+		log("        disables dff -> dffe conversion, and other transforms recognizing clock\n");
+		log("        enable\n");
 		log("\n");
 		log("    -nosdff\n");
-		log("        disables dff -> sdff conversion, and other transforms recognizing sync resets\n");
+		log("        disables dff -> sdff conversion, and other transforms recognizing sync\n");
+		log("        resets\n");
 		log("\n");
 		log("    -simple-dffe\n");
 		log("        only enables clock enable recognition transform for obvious cases\n");
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index a66a06586..eebd30017 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -196,9 +196,9 @@ struct XilinxSrlPass : public Pass {
 		log("\n");
 		log("This pass converts chains of built-in flops (bit-level: $_DFF_[NP]_, $_DFFE_*\n");
 		log("and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a\n");
-		log("$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock polarity,\n");
-		log("enable, and enable polarity (where relevant).\n");
-		log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred.");
+		log("$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock\n");
+		log("polarity, enable, and enable polarity (where relevant).\n");
+		log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred.\n");
 		log("\n");
 		log("    -minlen N\n");
 		log("        min length of shift register (default = 3)\n");
diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc
index 1302b3383..4580f194e 100644
--- a/passes/sat/qbfsat.cc
+++ b/passes/sat/qbfsat.cc
@@ -508,11 +508,11 @@ struct QbfSatPass : public Pass {
 		log("\n");
 		log("    qbfsat [options] [selection]\n");
 		log("\n");
-		log("This command solves an \"exists-forall\" 2QBF-SAT problem defined over the currently\n");
-		log("selected module. Existentially-quantified variables are declared by assigning a wire\n");
-		log("\"$anyconst\". Universally-quantified variables may be explicitly declared by assigning\n");
-		log("a wire \"$allconst\", but module inputs will be treated as universally-quantified\n");
-		log("variables by default.\n");
+		log("This command solves an \"exists-forall\" 2QBF-SAT problem defined over the\n");
+		log("currently selected module. Existentially-quantified variables are declared by\n");
+		log("assigning a wire \"$anyconst\". Universally-quantified variables may be\n");
+		log("explicitly declared by assigning a wire \"$allconst\", but module inputs will be\n");
+		log("treated as universally-quantified variables by default.\n");
 		log("\n");
 		log("    -nocleanup\n");
 		log("        Do not delete temporary files and directories. Useful for debugging.\n");
@@ -521,23 +521,25 @@ struct QbfSatPass : public Pass {
 		log("        Pass the --dump-smt2 option to yosys-smtbmc.\n");
 		log("\n");
 		log("    -assume-outputs\n");
-		log("        Add an \"$assume\" cell for the conjunction of all one-bit module output wires.\n");
+		log("        Add an \"$assume\" cell for the conjunction of all one-bit module output\n");
+		log("        wires.\n");
 		log("\n");
 		log("    -assume-negative-polarity\n");
-		log("        When adding $assume cells for one-bit module output wires, assume they are\n");
-		log("        negative polarity signals and should always be low, for example like the\n");
-		log("        miters created with the `miter` command.\n");
+		log("        When adding $assume cells for one-bit module output wires, assume they\n");
+		log("        are negative polarity signals and should always be low, for example like\n");
+		log("        the miters created with the `miter` command.\n");
 		log("\n");
 		log("    -nooptimize\n");
-		log("        Ignore \"\\minimize\" and \"\\maximize\" attributes, do not emit \"(maximize)\" or\n");
-		log("        \"(minimize)\" in the SMT-LIBv2, and generally make no attempt to optimize anything.\n");
+		log("        Ignore \"\\minimize\" and \"\\maximize\" attributes, do not emit\n");
+		log("        \"(maximize)\" or \"(minimize)\" in the SMT-LIBv2, and generally make no\n");
+		log("        attempt to optimize anything.\n");
 		log("\n");
 		log("    -nobisection\n");
-		log("        If a wire is marked with the \"\\minimize\" or \"\\maximize\" attribute, do not\n");
-		log("        attempt to optimize that value with the default iterated solving and threshold\n");
-		log("        bisection approach. Instead, have yosys-smtbmc emit a \"(minimize)\" or \"(maximize)\"\n");
-		log("        command in the SMT-LIBv2 output and hope that the solver supports optimizing\n");
-		log("        quantified bitvector problems.\n");
+		log("        If a wire is marked with the \"\\minimize\" or \"\\maximize\" attribute,\n");
+		log("        do not attempt to optimize that value with the default iterated solving\n");
+		log("        and threshold bisection approach. Instead, have yosys-smtbmc emit a\n");
+		log("        \"(minimize)\" or \"(maximize)\" command in the SMT-LIBv2 output and\n");
+		log("        hope that the solver supports optimizing quantified bitvector problems.\n");
 		log("\n");
 		log("    -solver <solver>\n");
 		log("        Use a particular solver. Choose one of: \"z3\", \"yices\", and \"cvc4\".\n");
@@ -567,13 +569,14 @@ struct QbfSatPass : public Pass {
 		log("        corresponding constant value from the model produced by the solver.\n");
 		log("\n");
 		log("    -specialize-from-file <solution file>\n");
-		log("        Do not run the solver, but instead only attempt to replace each \"$anyconst\"\n");
-		log("        cell in the current module with a constant value provided by the specified file.\n");
+		log("        Do not run the solver, but instead only attempt to replace each\n");
+		log("        \"$anyconst\" cell in the current module with a constant value provided\n");
+		log("        by the specified file.\n");
 		log("\n");
 		log("    -write-solution <solution file>\n");
-		log("        If the problem is satisfiable, write the corresponding constant value for each\n");
-		log("        \"$anyconst\" cell from the model produced by the solver to the specified file.");
-		log("\n");
+		log("        If the problem is satisfiable, write the corresponding constant value\n");
+		log("        for each \"$anyconst\" cell from the model produced by the solver to the\n");
+		log("        specified file.\n");
 		log("\n");
 	}
 
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 18a25a097..b68783f20 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -2013,7 +2013,8 @@ struct SimPass : public Pass {
 		log("        writeback mode: use final simulation state as new init state\n");
 		log("\n");
 		log("    -r\n");
-		log("        read simulation results file (file formats supported: FST, VCD, AIW and WIT)\n");
+		log("        read simulation results file\n");
+		log("            File formats supported: FST, VCD, AIW and WIT\n");
 		log("		 VCD support requires vcd2fst external tool to be present\n");
 		log("\n");
 		log("    -map <filename>\n");
@@ -2248,8 +2249,8 @@ struct Fst2TbPass : public Pass {
 		log("\n");
 		log("    fst2tb [options] [top-level]\n");
 		log("\n");
-		log("This command generates testbench for the circuit using the given top-level module\n");
-		log("and simulus signal from FST file\n");
+		log("This command generates testbench for the circuit using the given top-level\n");
+		log("module and simulus signal from FST file\n");
 		log("\n");
 		log("    -tb <name>\n");
 		log("        generated testbench name.\n");
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 656c36b84..4039336dd 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1532,7 +1532,8 @@ struct AbcPass : public Pass {
 		log("           NMUX, AOI3, OAI3, AOI4, OAI4.\n");
 		log("        (The NOT gate is always added to this list automatically.)\n");
 		log("\n");
-		log("        The following aliases can be used to reference common sets of gate types:\n");
+		log("        The following aliases can be used to reference common sets of gate\n");
+		log("        types:\n");
 		log("          simple: AND OR XOR MUX\n");
 		log("          cmos2:  NAND NOR\n");
 		log("          cmos3:  NAND NOR AOI3 OAI3\n");
@@ -1576,8 +1577,8 @@ struct AbcPass : public Pass {
 		log("\n");
 		log("    -dress\n");
 		log("        run the 'dress' command after all other ABC commands. This aims to\n");
-		log("        preserve naming by an equivalence check between the original and post-ABC\n");
-		log("        netlists (experimental).\n");
+		log("        preserve naming by an equivalence check between the original and\n");
+		log("        post-ABC netlists (experimental).\n");
 		log("\n");
 		log("When no target cell library is specified the Yosys standard cell library is\n");
 		log("loaded into ABC before the ABC script is executed.\n");
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 79c994b11..88fac67e8 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -93,8 +93,8 @@ struct Abc9Pass : public ScriptPass
 		log("\n");
 		log("    abc9 [options] [selection]\n");
 		log("\n");
-		log("This script pass performs a sequence of commands to facilitate the use of the ABC\n");
-		log("tool [1] for technology mapping of the current design to a target FPGA\n");
+		log("This script pass performs a sequence of commands to facilitate the use of the\n");
+		log("ABC tool [1] for technology mapping of the current design to a target FPGA\n");
 		log("architecture. Only fully-selected modules are supported.\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc
index 2f46c89f4..1d9bb4332 100644
--- a/passes/techmap/abc9_exe.cc
+++ b/passes/techmap/abc9_exe.cc
@@ -303,8 +303,8 @@ struct Abc9ExePass : public Pass {
 		log("\n");
 		log(" \n");
 		log("This pass uses the ABC tool [1] for technology mapping of the top module\n");
-		log("(according to the (* top *) attribute or if only one module is currently selected)\n");
-		log("to a target FPGA architecture.\n");
+		log("(according to the (* top *) attribute or if only one module is currently\n");
+		log("selected) to a target FPGA architecture.\n");
 		log("\n");
 		log("    -exe <command>\n");
 #ifdef ABCEXTERNAL
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index acafb0b65..9766e81cb 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1572,14 +1572,14 @@ struct Abc9OpsPass : public Pass {
 		log("the `abc9' script pass. Only fully-selected modules are supported.\n");
 		log("\n");
 		log("    -check\n");
-		log("        check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
-		log("        (* abc9_carry *) is only given for one input/output port, etc.\n");
+		log("        check that the design is valid, e.g. (* abc9_box_id *) values are\n");
+		log("        unique, (* abc9_carry *) is only given for one input/output port, etc.\n");
 		log("\n");
 		log("    -prep_hier\n");
 		log("        derive all used (* abc9_box *) or (* abc9_flop *) (if -dff option)\n");
 		log("        whitebox modules. with (* abc9_flop *) modules, only those containing\n");
-		log("        $dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC limitation\n");
-		log("        -- will be derived.\n");
+		log("        $dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC\n");
+		log("        limitation -- will be derived.\n");
 		log("\n");
 		log("    -prep_bypass\n");
 		log("        create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for\n");
@@ -1597,33 +1597,35 @@ struct Abc9OpsPass : public Pass {
 		log("    -prep_dff_submod\n");
 		log("        within (* abc9_flop *) modules, rewrite all edge-sensitive path\n");
 		log("        declarations and $setup() timing checks ($specify3 and $specrule cells)\n");
-		log("        that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port to\n");
-		log("        the DFF's 'D' port. this is to prepare such specify cells to be moved\n");
+		log("        that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port\n");
+		log("        to the DFF's 'D' port. this is to prepare such specify cells to be moved\n");
 		log("        into the flop box.\n");
 		log("\n");
 		log("    -prep_dff_unmap\n");
-		log("        populate the '$abc9_unmap' design with techmap rules for mapping *_$abc9_flop\n");
-		log("        cells back into their derived cell types (where the rules created by\n");
-		log("        -prep_hier will then map back to the original cell with parameters).\n");
+		log("        populate the '$abc9_unmap' design with techmap rules for mapping\n");
+		log("        *_$abc9_flop cells back into their derived cell types (where the rules\n");
+		log("        created by -prep_hier will then map back to the original cell with\n");
+		log("        parameters).\n");
 		log("\n");
 		log("    -prep_delays\n");
 		log("        insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
 		log("        certain required times.\n");
 		log("\n");
 		log("    -break_scc\n");
-		log("        for an arbitrarily chosen cell in each unique SCC of each selected module\n");
-		log("        (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt all wires\n");
-		log("        driven by this cell's outputs with a temporary $__ABC9_SCC_BREAKER cell\n");
-		log("        to break the SCC.\n");
+		log("        for an arbitrarily chosen cell in each unique SCC of each selected\n");
+		log("        module (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt\n");
+		log("        all wires driven by this cell's outputs with a temporary\n");
+		log("        $__ABC9_SCC_BREAKER cell to break the SCC.\n");
 		log("\n");
 		log("    -prep_xaiger\n");
 		log("        prepare the design for XAIGER output. this includes computing the\n");
-		log("        topological ordering of ABC9 boxes, as well as preparing the '$abc9_holes'\n");
-		log("        design that contains the logic behaviour of ABC9 whiteboxes.\n");
+		log("        topological ordering of ABC9 boxes, as well as preparing the \n");
+		log("        '$abc9_holes' design that contains the logic behaviour of ABC9\n");
+		log("        whiteboxes.\n");
 		log("\n");
 		log("    -dff\n");
-		log("        consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
-		log("        during -prep_{delays,xaiger,box}.\n");
+		log("        consider flop cells (those instantiating modules marked with\n");
+		log("        (* abc9_flop *)) during -prep_{delays,xaiger,box}.\n");
 		log("\n");
 		log("    -prep_lut <maxlut>\n");
 		log("        pre-compute the lut library by analysing all modules marked with\n");
@@ -1641,8 +1643,8 @@ struct Abc9OpsPass : public Pass {
 		log("\n");
 		log("    -reintegrate\n");
 		log("        for each selected module, re-intergrate the module '<module-name>$abc9'\n");
-		log("        by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
-		log("        inputs and outputs.\n");
+		log("        by first recovering ABC9 boxes, and then stitching in the remaining\n");
+		log("        primary inputs and outputs.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc
index 1d99caa3a..c6c3a58c5 100644
--- a/passes/techmap/dfflegalize.cc
+++ b/passes/techmap/dfflegalize.cc
@@ -118,34 +118,24 @@ struct DffLegalizePass : public Pass {
 		log("- $_DLATCH_[NP][NP][01]_\n");
 		log("- $_DLATCHSR_[NP][NP][NP]_\n");
 		log("\n");
-		log("The following transformations are performed by this pass:");
-		log("\n");
-		log("- upconversion from a less capable cell to a more capable cell, if the less");
-		log("  capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)");
-		log("\n");
-		log("- unmapping FFs with clock enable (due to unsupported cell type or -mince)");
-		log("\n");
-		log("- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)");
-		log("\n");
-		log("- adding inverters on the control pins (due to unsupported polarity)");
+		log("The following transformations are performed by this pass:\n");
 		log("\n");
+		log("- upconversion from a less capable cell to a more capable cell, if the less\n");
+		log("  capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)\n");
+		log("- unmapping FFs with clock enable (due to unsupported cell type or -mince)\n");
+		log("- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)\n");
+		log("- adding inverters on the control pins (due to unsupported polarity)\n");
 		log("- adding inverters on the D and Q pins and inverting the init/reset values\n");
-		log("  (due to unsupported init or reset value)");
-		log("\n");
-		log("- converting sr into adlatch (by tying D to 1 and using E as set input)");
-		log("\n");
-		log("- emulating unsupported dffsr cell by adff + adff + sr + mux");
-		log("\n");
-		log("- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux");
-		log("\n");
+		log("  (due to unsupported init or reset value)\n");
+		log("- converting sr into adlatch (by tying D to 1 and using E as set input)\n");
+		log("- emulating unsupported dffsr cell by adff + adff + sr + mux\n");
+		log("- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux\n");
 		log("- emulating adff when the (reset, init) value combination is unsupported by\n");
-		log("  dff + adff + dlatch + mux");
-		log("\n");
+		log("  dff + adff + dlatch + mux\n");
 		log("- emulating adlatch when the (reset, init) value combination is unsupported by\n");
-		log("- dlatch + adlatch + dlatch + mux");
-		log("\n");
-		log("If the pass is unable to realize a given cell type (eg. adff when only plain dff");
-		log("is available), an error is raised.");
+		log("- dlatch + adlatch + dlatch + mux\n");
+		log("If the pass is unable to realize a given cell type (eg. adff when only plain dff\n");
+		log("is available), an error is raised.\n");
 	}
 
 	// Table of all supported cell types.
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 252baae9a..12c3a95de 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -431,7 +431,7 @@ struct DfflibmapPass : public Pass {
 		log("cells, leaving remaining internal cells untouched.\n");
 		log("\n");
 		log("When called with -info, this command will only print the target cell\n");
-		log("list, along with their associated internal cell types, and the arguments");
+		log("list, along with their associated internal cell types, and the arguments\n");
 		log("that would be passed to the dfflegalize pass.  The design will not be\n");
 		log("changed.\n");
 		log("\n");
diff --git a/passes/techmap/dffunmap.cc b/passes/techmap/dffunmap.cc
index 7312015f1..8703bf1a0 100644
--- a/passes/techmap/dffunmap.cc
+++ b/passes/techmap/dffunmap.cc
@@ -33,8 +33,8 @@ struct DffunmapPass : public Pass {
 		log("    dffunmap [options] [selection]\n");
 		log("\n");
 		log("This pass transforms FF types with clock enable and/or synchronous reset into\n");
-		log("their base type (with neither clock enable nor sync reset) by emulating the clock\n");
-		log("enable and synchronous reset with multiplexers on the cell input.\n");
+		log("their base type (with neither clock enable nor sync reset) by emulating the\n");
+		log("clock enable and synchronous reset with multiplexers on the cell input.\n");
 		log("\n");
 		log("    -ce-only\n");
 		log("        unmap only clock enables, leave synchronous resets alone.\n");
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 7d8dba439..f75b82919 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -476,7 +476,8 @@ struct SimplemapPass : public Pass {
 		log("  $not, $pos, $and, $or, $xor, $xnor\n");
 		log("  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
 		log("  $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
-		log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
+		log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff,\n");
+		log("  $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 5cd78fe28..144f596c8 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1026,8 +1026,8 @@ struct TechmapPass : public Pass {
 		log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
 		log("match cells with a type that match the text value of this attribute. Otherwise\n");
 		log("the module name will be used to match the cell.  Multiple space-separated cell\n");
-		log("types can be listed, and wildcards using [] will be expanded (ie. \"$_DFF_[PN]_\"\n");
-		log("is the same as \"$_DFF_P_ $_DFF_N_\").\n");
+		log("types can be listed, and wildcards using [] will be expanded (ie.\n");
+		log("\"$_DFF_[PN]_\" is the same as \"$_DFF_P_ $_DFF_N_\").\n");
 		log("\n");
 		log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
 		log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
@@ -1083,11 +1083,11 @@ struct TechmapPass : public Pass {
 		log("        It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
 		log("\n");
 		log("    _TECHMAP_REMOVEINIT_<port-name>_\n");
-		log("        When this wire is set to a constant value, the init attribute of the wire(s)\n");
-		log("        connected to this port will be consumed.  This wire must have the same\n");
-		log("        width as the given port, and for every bit that is set to 1 in the value,\n");
-		log("        the corresponding init attribute bit will be changed to 1'bx.  If all\n");
-		log("        bits of an init attribute are left as x, it will be removed.\n");
+		log("        When this wire is set to a constant value, the init attribute of the\n");
+		log("        wire(s) connected to this port will be consumed.  This wire must have\n");
+		log("        the same width as the given port, and for every bit that is set to 1 in\n");
+		log("        the value, the corresponding init attribute bit will be changed to 1'bx.\n");
+		log("        If all bits of an init attribute are left as x, it will be removed.\n");
 		log("\n");
 		log("In addition to this special wires, techmap also supports special parameters in\n");
 		log("modules in the map file:\n");
@@ -1108,8 +1108,8 @@ struct TechmapPass : public Pass {
 		log("\n");
 		log("    _TECHMAP_WIREINIT_<port-name>_\n");
 		log("        When a parameter with this name exists, it will be set to the initial\n");
-		log("        value of the wire(s) connected to the given port, as specified by the init\n");
-		log("        attribute. If the attribute doesn't exist, x will be filled for the\n");
+		log("        value of the wire(s) connected to the given port, as specified by the\n");
+		log("        init attribute. If the attribute doesn't exist, x will be filled for the\n");
 		log("        missing bits.  To remove the init attribute bits used, use the\n");
 		log("        _TECHMAP_REMOVEINIT_*_ wires.\n");
 		log("\n");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 1174f6e04..2ae859efe 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -45,8 +45,8 @@ struct SynthIce40Pass : public ScriptPass
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
 		log("    -device < hx | lp | u >\n");
-		log("        relevant only for '-abc9' flow, optimise timing for the specified device.\n");
-		log("        default: hx\n");
+		log("        relevant only for '-abc9' flow, optimise timing for the specified\n");
+		log("        device. default: hx\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 166c81843..e9594e6d8 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -39,21 +39,22 @@ struct SynthIntelPass : public ScriptPass {
 		log("    -family <max10 | cyclone10lp | cycloneiv | cycloneive>\n");
 		log("        generate the synthesis netlist for the specified family.\n");
 		log("        MAX10 is the default target if no family argument specified.\n");
-		log("        For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
-		log("        For Cyclone V and Cyclone 10 GX, use the synth_intel_alm backend instead.\n");
+		log("        For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use\n");
+		log("        cycloneive. For Cyclone V and Cyclone 10 GX, use the synth_intel_alm\n");
+		log("        backend instead.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module (default='top')\n");
 		log("\n");
 		log("    -vqm <file>\n");
-		log("        write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
-		log("        output file is omitted if this parameter is not specified.\n");
+		log("        write the design to the specified Verilog Quartus Mapping File. Writing\n");
+		log("        of an output file is omitted if this parameter is not specified.\n");
 		log("        Note that this backend has not been tested and is likely incompatible\n");
 		log("        with recent versions of Quartus.\n");
 		log("\n");
 		log("    -vpr <file>\n");
-		log("        write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
-		log("        compatible with the Quartus flow. Writing of an\n");
+		log("        write BLIF files for VPR flow experiments. The synthesized BLIF output\n");
+		log("        file is not compatible with the Quartus flow. Writing of an\n");
 		log("        output file is omitted if this parameter is not specified.\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 43d3592d5..c33eb43bf 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -43,21 +43,24 @@ struct SynthIntelALMPass : public ScriptPass {
 		log("    -family <family>\n");
 		log("        target one of:\n");
 		log("        \"cyclonev\"    - Cyclone V (default)\n");
-		log("        \"arriav\"      - Arria V (non-GZ)");
+		log("        \"arriav\"      - Arria V (non-GZ)\n");
 		log("        \"cyclone10gx\" - Cyclone 10GX\n");
 		log("\n");
 		log("    -vqm <file>\n");
-		log("        write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
-		log("        output file is omitted if this parameter is not specified. Implies -quartus.\n");
+		log("        write the design to the specified Verilog Quartus Mapping File. Writing\n");
+		log("        of an output file is omitted if this parameter is not specified. Implies\n");
+		log("        -quartus.\n");
 		log("\n");
 		log("    -noflatten\n");
-		log("        do not flatten design before synthesis; useful for per-module area statistics\n");
+		log("        do not flatten design before synthesis; useful for per-module area\n");
+		log("        statistics\n");
 		log("\n");
 		log("    -quartus\n");
 		log("        output a netlist using Quartus cells instead of MISTRAL_* cells\n");
 		log("\n");
 		log("    -dff\n");
-		log("        pass DFFs to ABC to perform sequential logic optimisations (EXPERIMENTAL)\n");
+		log("        pass DFFs to ABC to perform sequential logic optimisations\n");
+		log("        (EXPERIMENTAL)\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");
diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc
index 754de2de6..94bd44db0 100644
--- a/techlibs/quicklogic/synth_quicklogic.cc
+++ b/techlibs/quicklogic/synth_quicklogic.cc
@@ -48,8 +48,8 @@ struct SynthQuickLogicPass : public ScriptPass {
 		log("        is omitted if this parameter is not specified.\n");
 		log("\n");
 		log("    -verilog <file>\n");
-		log("        write the design to the specified verilog file. writing of an output file\n");
-		log("        is omitted if this parameter is not specified.\n");
+		log("        write the design to the specified verilog file. writing of an output\n");
+		log("        file is omitted if this parameter is not specified.\n");
 		log("\n");
 		log("    -abc\n");
 		log("        use old ABC flow, which has generally worse mapping results but is less\n");
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 8d78a6097..f78b4f012 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -45,8 +45,8 @@ struct SynthSf2Pass : public ScriptPass
 		log("        is omitted if this parameter is not specified.\n");
 		log("\n");
 		log("    -vlog <file>\n");
-		log("        write the design to the specified Verilog file. writing of an output file\n");
-		log("        is omitted if this parameter is not specified.\n");
+		log("        write the design to the specified Verilog file. writing of an output\n");
+		log("        file is omitted if this parameter is not specified.\n");
 		log("\n");
 		log("    -json <file>\n");
 		log("        write the design to the specified JSON file. writing of an output file\n");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6214e1411..a242cdef1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -93,7 +93,8 @@ struct SynthXilinxPass : public ScriptPass
 		log("        do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
 		log("\n");
 		log("    -nowidelut\n");
-		log("        do not use MUXF[5-9] resources to implement LUTs larger than native for the target\n");
+		log("        do not use MUXF[5-9] resources to implement LUTs larger than native for\n");
+		log("        the target\n");
 		log("\n");
 		log("    -nodsp\n");
 		log("        do not use DSP48*s to implement multipliers and associated logic\n");
@@ -109,8 +110,8 @@ struct SynthXilinxPass : public ScriptPass
 		log("        infer URAM288s for large memories (xcup only)\n");
 		log("\n");
 		log("    -widemux <int>\n");
-		log("        enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
-		log("        above this number of inputs (minimum value 2, recommended value >= 5).\n");
+		log("        enable inference of hard multiplexer resources (MUXF[78]) for muxes at\n");
+		log("        or above this number of inputs (minimum value 2, recommended value >= 5)\n");
 		log("        default: 0 (no inference)\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
-- 
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