From 910556560fbf26df4f2960b7d94039a1f399f1a1 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 14 Feb 2015 10:23:03 +0100
Subject: Added $meminit cell type

---
 kernel/celltypes.h       |  1 +
 kernel/rtlil.cc          |  9 +++++++++
 passes/opt/opt_clean.cc  |  2 +-
 techlibs/common/simlib.v | 22 ++++++++++++++++++++++
 4 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 60e6606f8..57bcde471 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -135,6 +135,7 @@ struct CellTypes
 
 		setup_type("$memrd", {CLK, ADDR}, {DATA});
 		setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
+		setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
 		setup_type("$mem", {RD_CLK, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
 
 		setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 776625b9c..9fd3d2959 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -904,6 +904,15 @@ namespace {
 				return;
 			}
 
+			if (cell->type == "$meminit") {
+				param("\\MEMID");
+				param("\\PRIORITY");
+				port("\\ADDR", param("\\ABITS"));
+				port("\\DATA", param("\\WIDTH"));
+				check_expected();
+				return;
+			}
+
 			if (cell->type == "$mem") {
 				param("\\MEMID");
 				param("\\SIZE");
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 6a7e6051d..aea341759 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -47,7 +47,7 @@ void rmunused_module_cells(Module *module, bool verbose)
 					if (bit.wire != nullptr)
 						wire2driver[bit].insert(cell);
 		}
-		if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr())
+		if (cell->type.in("$memwr", "$meminit", "$assert") || cell->has_keep_attr())
 			queue.insert(cell);
 		else
 			unused.insert(cell);
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a73c6ee09..6707e190b 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1514,6 +1514,28 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$meminit (ADDR, DATA);
+
+parameter MEMID = "";
+parameter ABITS = 8;
+parameter WIDTH = 8;
+
+parameter PRIORITY = 0;
+
+input [ABITS-1:0] ADDR;
+input [WIDTH-1:0] DATA;
+
+initial begin
+	if (MEMID != "") begin
+		$display("ERROR: Found non-simulatable instance of $meminit!");
+		$finish;
+	end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
 
 parameter MEMID = "";
-- 
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