From 5aa8d7ceeb663be24c7b815822d0de2ee25431a6 Mon Sep 17 00:00:00 2001
From: Diego H <diego@symbioticeda.com>
Date: Mon, 2 Sep 2019 17:43:27 -0500
Subject: Updating gowin

---
 techlibs/gowin/arith_map.v    | 2 +-
 techlibs/gowin/synth_gowin.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
index e15de6423..af805b254 100644
--- a/techlibs/gowin/arith_map.v
+++ b/techlibs/gowin/arith_map.v
@@ -45,7 +45,7 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
 
    genvar 		i;
    generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-      ALU #(.ALU_MODE(32'b0))
+      ALU #(.ALU_MODE(0))
       alu(.I0(AA[i]),
 	  .I1(BB[i]),
 	  .I3(1'b0),
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index ac3dbfb29..1fc029e3c 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -226,7 +226,7 @@ struct SynthGowinPass : public ScriptPass
 		if (check_label("vout"))
 		{
 			if (!vout_file.empty() || help_mode)
-				run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s",
+				 run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s",
 						help_mode ? "<file-name>" : vout_file.c_str()));
 		}
 	}
-- 
cgit v1.2.3


From ec56438cf29c6cfdad5cc28987298ec6bd363d47 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 4 Sep 2019 10:33:47 +0200
Subject: gowin: add splitnets to appease the PnR

---
 techlibs/gowin/synth_gowin.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index ac3dbfb29..9c2a5c837 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -186,6 +186,7 @@ struct SynthGowinPass : public ScriptPass
 			run("techmap -map +/techmap.v");
 			if (retime || help_mode)
 				run("abc -dff", "(only if -retime)");
+			run("splitnets");
 		}
 
 		if (check_label("map_ffs"))
-- 
cgit v1.2.3


From 6cf5157fe7a8f4299a002f1be6c95ba5507a2cd4 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 4 Sep 2019 10:52:28 +0200
Subject: Update example for GW1NR-9

This uses the Trenz TEC0117 on Gowin IDE 1.8.4
---
 examples/gowin/demo.cst   | 51 ++++++++++-------------------------------------
 examples/gowin/demo.v     |  5 +----
 examples/gowin/device.cfg | 16 +++++++++++++++
 examples/gowin/run.sh     |  3 +--
 4 files changed, 28 insertions(+), 47 deletions(-)
 create mode 100644 examples/gowin/device.cfg

diff --git a/examples/gowin/demo.cst b/examples/gowin/demo.cst
index 22d7eb668..c8f89dcf8 100644
--- a/examples/gowin/demo.cst
+++ b/examples/gowin/demo.cst
@@ -1,41 +1,10 @@
-// 50 MHz Clock
-IO_LOC "clk" D11;
-
-// LEDs
-IO_LOC "leds[0]"  D22;
-IO_LOC "leds[1]"  E22;
-IO_LOC "leds[2]"  G22;
-IO_LOC "leds[3]"  J22;
-IO_LOC "leds[4]"  L22;
-IO_LOC "leds[5]"  L19;
-IO_LOC "leds[6]"  L20;
-IO_LOC "leds[7]"  M21;
-IO_LOC "leds[8]"  N19;
-IO_LOC "leds[9]"  R19;
-IO_LOC "leds[10]" T18;
-IO_LOC "leds[11]" AA22;
-IO_LOC "leds[12]" U18;
-IO_LOC "leds[13]" V20;
-IO_LOC "leds[14]" AA21;
-IO_LOC "leds[15]" AB21;
-
-
-// 7-Segment Display
-IO_LOC "seg7dig[0]" E20;
-IO_LOC "seg7dig[1]" G18;
-IO_LOC "seg7dig[2]" G20;
-IO_LOC "seg7dig[3]" F21;
-IO_LOC "seg7dig[4]" J20;
-IO_LOC "seg7dig[5]" H21;
-IO_LOC "seg7dig[6]" H18;
-IO_LOC "seg7dig[7]" D20;
-IO_LOC "seg7sel[0]" C19;
-IO_LOC "seg7sel[1]" B22;
-IO_LOC "seg7sel[2]" C20;
-IO_LOC "seg7sel[3]" C21;
-
-// Switches
-IO_LOC "sw[0]" AB20;
-IO_LOC "sw[1]" AB19;
-IO_LOC "sw[2]" AB18;
-IO_LOC "sw[3]" AB17;
+IO_LOC "clk" 35;
+//IO_LOC "rst_n" 77;
+IO_LOC "leds[0]" 79;
+IO_LOC "leds[1]" 80;
+IO_LOC "leds[2]" 81;
+IO_LOC "leds[3]" 82;
+IO_LOC "leds[4]" 83;
+IO_LOC "leds[5]" 84;
+IO_LOC "leds[6]" 85;
+IO_LOC "leds[7]" 86;
\ No newline at end of file
diff --git a/examples/gowin/demo.v b/examples/gowin/demo.v
index 6ea108384..3cb782fa7 100644
--- a/examples/gowin/demo.v
+++ b/examples/gowin/demo.v
@@ -1,9 +1,6 @@
 module demo (
 	input clk,
-	input [3:0] sw,
-	output [15:0] leds,
-	output [7:0] seg7dig,
-	output [3:0] seg7sel
+	output [15:0] leds
 );
 	localparam PRESCALE = 20;
 	reg [PRESCALE+3:0] counter = 0;
diff --git a/examples/gowin/device.cfg b/examples/gowin/device.cfg
new file mode 100644
index 000000000..f6ab82159
--- /dev/null
+++ b/examples/gowin/device.cfg
@@ -0,0 +1,16 @@
+set JTAG regular_io = false
+set SSPI regular_io = false
+set MSPI regular_io = false
+set READY regular_io = false
+set DONE regular_io = false
+set RECONFIG_N regular_io = false
+set MODE regular_io = false
+set CRC_check = true
+set compress = false
+set encryption = false
+set security_bit_enable = true
+set bsram_init_fuse_print = true
+set download_speed = 250/100
+set spi_flash_address = 0x00FFF000
+set format = txt
+set background_programming = false
diff --git a/examples/gowin/run.sh b/examples/gowin/run.sh
index 33a7b5c37..cd260101e 100644
--- a/examples/gowin/run.sh
+++ b/examples/gowin/run.sh
@@ -1,8 +1,7 @@
 #!/bin/bash
 set -ex
 yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v
-$GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW2A55-PBGA484-6 \
-		-warning_all -out demo_out.v -rpt demo.rpt -tr demo_tr.html -bit demo.bit
+$GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW1NR-9-QFN88-6 -pn GW1NR-LV9QN88C6/I5 -cfg device.cfg -bit -tr -ph -timing -gpa -rpt -warning_all
 
 # post place&route simulation (icarus verilog)
 if false; then
-- 
cgit v1.2.3


From 072367245184528de0907f48ed45af79901d93eb Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 4 Sep 2019 10:58:48 +0200
Subject: Add demonstration of breakage

Unused outputs lead to undriven buffers, which lead to syntax errors.
---
 examples/gowin/demo.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/examples/gowin/demo.v b/examples/gowin/demo.v
index 3cb782fa7..f5c001893 100644
--- a/examples/gowin/demo.v
+++ b/examples/gowin/demo.v
@@ -1,6 +1,7 @@
 module demo (
 	input clk,
 	output [15:0] leds
+	//,output unused
 );
 	localparam PRESCALE = 20;
 	reg [PRESCALE+3:0] counter = 0;
-- 
cgit v1.2.3


From 06062090dacf868b2a4eda32152c188a1b8be089 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 4 Sep 2019 14:47:59 +0200
Subject: add broken TCL run script

---
 examples/gowin/pnr.cfg |  8 ++++++++
 examples/gowin/run.tcl | 10 ++++++++++
 2 files changed, 18 insertions(+)
 create mode 100644 examples/gowin/pnr.cfg
 create mode 100644 examples/gowin/run.tcl

diff --git a/examples/gowin/pnr.cfg b/examples/gowin/pnr.cfg
new file mode 100644
index 000000000..a1b43cc3b
--- /dev/null
+++ b/examples/gowin/pnr.cfg
@@ -0,0 +1,8 @@
+-sdf
+-oc
+-ibs
+-posp
+-o
+-warning_all
+-tt
+-timing
diff --git a/examples/gowin/run.tcl b/examples/gowin/run.tcl
new file mode 100644
index 000000000..7bb5648e5
--- /dev/null
+++ b/examples/gowin/run.tcl
@@ -0,0 +1,10 @@
+# gw_sh run.tcl
+exec yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v
+add_file -cst demo.cst
+add_file -sdc demo.sdc
+add_file -vm demo_syn.v
+add_file -cfg device.cfg
+add_setting -pnr pnr.cfg
+set_option -device GW1NR-9-QFN88-6
+set_option -pn GW1NR-LV9QN88C6/I5
+run_pnr
-- 
cgit v1.2.3


From d65a47c86d4ccc89db419638896fefd3b2324588 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 4 Sep 2019 15:35:33 +0200
Subject: fix tcl script

---
 examples/gowin/run.tcl | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/examples/gowin/run.tcl b/examples/gowin/run.tcl
index 7bb5648e5..39da11cee 100644
--- a/examples/gowin/run.tcl
+++ b/examples/gowin/run.tcl
@@ -4,7 +4,6 @@ add_file -cst demo.cst
 add_file -sdc demo.sdc
 add_file -vm demo_syn.v
 add_file -cfg device.cfg
-add_setting -pnr pnr.cfg
 set_option -device GW1NR-9-QFN88-6
 set_option -pn GW1NR-LV9QN88C6/I5
-run_pnr
+run_pnr -opt pnr.cfg
-- 
cgit v1.2.3


From ae93c034adc8a7d14a9f39175dacdddda75ea7a2 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 4 Sep 2019 16:29:40 +0200
Subject: set undriven pads to zero

---
 examples/gowin/demo.v         | 4 ++--
 techlibs/gowin/synth_gowin.cc | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/examples/gowin/demo.v b/examples/gowin/demo.v
index f5c001893..485fec97f 100644
--- a/examples/gowin/demo.v
+++ b/examples/gowin/demo.v
@@ -1,7 +1,7 @@
 module demo (
 	input clk,
-	output [15:0] leds
-	//,output unused
+	output [15:0] leds,
+	output unused
 );
 	localparam PRESCALE = 20;
 	reg [PRESCALE+3:0] counter = 0;
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 0bfa9da1a..f7a5006bc 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -210,6 +210,7 @@ struct SynthGowinPass : public ScriptPass
 		if (check_label("map_cells"))
 		{
 			run("techmap -map +/gowin/cells_map.v");
+			run("setundef -undriven -zero");
 			run("hilomap -hicell VCC V -locell GND G");
 			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
 			run("dffinit  -ff DFF Q INIT");
-- 
cgit v1.2.3


From 3eff2271d0fe25632f7e6b22cf0be078d2cd9990 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Thu, 5 Sep 2019 13:36:41 +0200
Subject: add MUX support

---
 techlibs/gowin/cells_map.v    |  3 +++
 techlibs/gowin/cells_sim.v    | 13 +++++++++++++
 techlibs/gowin/synth_gowin.cc |  1 +
 3 files changed, 17 insertions(+)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index ebdc88a0a..c38805b91 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -5,6 +5,9 @@ module  \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D),
 module  \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
 module  \$__DFFS_PP1_ (input D, C, R, output Q); DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
 
+module  \$_MUX_ (input A, B, S, output Y); MUX2  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule
+module  \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule
+
 module \$lut (A, Y);
   parameter WIDTH = 0;
   parameter LUT = 0;
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index ebb238bad..98dfef9bf 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -24,6 +24,19 @@ module LUT4(output F, input I0, I1, I2, I3);
 	assign F = I0 ? s1[1] : s1[0];
 endmodule
 
+module MUX2 (I0, I1, S0, O);
+input I0, I1, S0;
+output O;
+assign O = S0 ? I1 : I0;
+endmodule
+
+module MUX4 (I0, I1, I2, I3, S0, S1, O);
+input I0, I1, I2, I3, S0, S1;
+output O;
+assign O = S1 ? (S0 ? I3 : I2) :
+                (S0 ? I1 : I0);
+endmodule
+
 module DFF (output reg Q, input CLK, D);
 	parameter [0:0] INIT = 1'b0;
 	initial Q = INIT;
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index f7a5006bc..4d32f62d4 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -196,6 +196,7 @@ struct SynthGowinPass : public ScriptPass
 			run("opt_clean");
 			if (!nodffe)
 				run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
+			run("muxcover -mux4");
 			run("techmap -map +/gowin/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
-- 
cgit v1.2.3


From 7a43be5e431f7518203b37bad2eb9ffb3b74add4 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Thu, 5 Sep 2019 16:38:47 +0200
Subject: use singleton ground and vcc nets, apparently this makes pnr happier

---
 techlibs/gowin/synth_gowin.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 4d32f62d4..3581d050e 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -212,7 +212,7 @@ struct SynthGowinPass : public ScriptPass
 		{
 			run("techmap -map +/gowin/cells_map.v");
 			run("setundef -undriven -zero");
-			run("hilomap -hicell VCC V -locell GND G");
+			run("hilomap -singleton -hicell VCC V -locell GND G");
 			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
 			run("dffinit  -ff DFF Q INIT");
 			run("clean");
-- 
cgit v1.2.3


From 47374a495d3cbfa424cbe312aa4762e7c4e855ff Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Thu, 5 Sep 2019 17:25:51 +0200
Subject: support bram initialisation

---
 techlibs/gowin/Makefile.inc   | 10 ++++++++++
 techlibs/gowin/bram.txt       |  3 +--
 techlibs/gowin/brams_init.py  |  8 ++++++++
 techlibs/gowin/brams_map.v    |  5 +++++
 techlibs/gowin/synth_gowin.cc |  2 +-
 5 files changed, 25 insertions(+), 3 deletions(-)
 create mode 100755 techlibs/gowin/brams_init.py

diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc
index 6f2159349..d2853704b 100644
--- a/techlibs/gowin/Makefile.inc
+++ b/techlibs/gowin/Makefile.inc
@@ -15,3 +15,13 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt))
 
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh))
 
+EXTRA_OBJS += techlibs/gowin/brams_init.mk
+.SECONDARY: techlibs/gowin/brams_init.mk
+
+techlibs/gowin/brams_init.mk: techlibs/gowin/brams_init.py
+	$(Q) mkdir -p techlibs/gowin
+	$(P) python3 $<
+	$(Q) touch $@
+
+techlibs/gowin/bram_init_16.vh: techlibs/gowin/brams_init.mk
+$(eval $(call add_gen_share_file,share/gowin,techlibs/gowin/bram_init_16.vh))
diff --git a/techlibs/gowin/bram.txt b/techlibs/gowin/bram.txt
index b5f9a981c..366a7106e 100644
--- a/techlibs/gowin/bram.txt
+++ b/techlibs/gowin/bram.txt
@@ -1,6 +1,5 @@
 bram $__GW1NR_SDP
-# uncomment when done
-#  init 1
+  init 1
   abits 10 @a10d18
   dbits 16 @a10d18
   abits 11 @a11d9
diff --git a/techlibs/gowin/brams_init.py b/techlibs/gowin/brams_init.py
new file mode 100755
index 000000000..b78eb8da5
--- /dev/null
+++ b/techlibs/gowin/brams_init.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3
+
+with open("techlibs/gowin/bram_init_16.vh", "w") as f:
+    for i in range(0, 0x40):
+        low = i << 8
+        hi = ((i+1) << 8)-1
+        snippet = "INIT[%d:%d]" % (hi, low)
+        print(".INIT_RAM_%02X({%s})," % (i, snippet), file=f)
diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v
index e963cfa88..c60330b4f 100644
--- a/techlibs/gowin/brams_map.v
+++ b/techlibs/gowin/brams_map.v
@@ -28,6 +28,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	
 	generate if (CFG_DBITS == 1) begin
 		SDP   #(
+      `include "bram_init_16.vh"
 			.READ_MODE(0),
 			.BIT_WIDTH_0(1),
 			.BIT_WIDTH_1(1),
@@ -42,6 +43,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 		);
 	end else if (CFG_DBITS == 2) begin
 		SDP    #(
+      `include "bram_init_16.vh"
 			.READ_MODE(0),
 			.BIT_WIDTH_0(2),
 			.BIT_WIDTH_1(2),
@@ -56,6 +58,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 		);
 	end else if (CFG_DBITS <= 4) begin
 		SDP    #(
+      `include "bram_init_16.vh"
 			.READ_MODE(0),
 			.BIT_WIDTH_0(4),
 			.BIT_WIDTH_1(4),
@@ -70,6 +73,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 		);
 	end else if (CFG_DBITS <= 8) begin
 		SDP    #(
+      `include "bram_init_16.vh"
 			.READ_MODE(0),
 			.BIT_WIDTH_0(8),
 			.BIT_WIDTH_1(8),
@@ -84,6 +88,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 		);
 	end else if (CFG_DBITS <= 16) begin
 		SDP    #(
+      `include "bram_init_16.vh"
 			.READ_MODE(0),
 			.BIT_WIDTH_0(16),
 			.BIT_WIDTH_1(16),
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 3581d050e..cfddcec12 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -229,7 +229,7 @@ struct SynthGowinPass : public ScriptPass
 		if (check_label("vout"))
 		{
 			if (!vout_file.empty() || help_mode)
-				 run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s",
+				 run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s",
 						help_mode ? "<file-name>" : vout_file.c_str()));
 		}
 	}
-- 
cgit v1.2.3


From 5168b6ffa4047340b3412aa17be7e2d7ac587ee1 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Thu, 5 Sep 2019 19:12:47 +0200
Subject: WIP aditional DFF primitives

---
 techlibs/gowin/cells_map.v | 47 +++++++++++++++++++++++++++++++++++++++++++++-
 techlibs/gowin/cells_sim.v |  2 ++
 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index c38805b91..aea11d97e 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -1,9 +1,54 @@
+// TODO add these DFF types
+// Primitive Description
+// DFFSE     D Flip-Flop with Clock Enable and Synchronous Set
+// DFFRE     D Flip-Flop with Clock Enable and Synchronous Reset
+
+// DFFNS     D Flip-Flop with Negative-Edge Clock and Synchronous Set
+// DFFNSE    D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
+// DFFNR     D Flip-Flop with Negative-Edge Clock and Synchronous Reset
+// DFFNRE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
+// DFFNP     D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
+// DFFNPE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
+// DFFNC     D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
+// DFFNCE    D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
+
+//TODO all DFF* have INIT
+
+// DFFN      D Flip-Flop with Negative-Edge Clock
 module  \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
+// DFF       D Flip-Flop
 module  \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF  #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
 
+// DFFE      D Flip-Flop with Clock Enable
+module  \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule
+
+// DFFNE     D Flip-Flop with Negative-Edge Clock and Clock Enable
+module  \$_DFFE_NP_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
+module  \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule
+
+// DFFR      D Flip-Flop with Synchronous Reset
 module  \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
 module  \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
-module  \$__DFFS_PP1_ (input D, C, R, output Q); DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
+
+// DFFS      D Flip-Flop with Synchronous Set
+module  \$__DFFS_PN1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!S)); endmodule
+module  \$__DFFS_PP1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(S)); endmodule
+
+// DFFP      D Flip-Flop with Asynchronous Preset
+module  \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule
+// DFFC      D Flip-Flop with Asynchronous Clear
+module  \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule
+
+// DFFPE     D Flip-Flop with Clock Enable and Asynchronous Preset
+module  \$__DFFE_PP1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
+module  \$__DFFE_PN1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
+// DFFCE     D Flip-Flop with Clock Enable and Asynchronous Clear
+module  \$__DFFE_PP0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
+module  \$__DFFE_PN0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
+
 
 module  \$_MUX_ (input A, B, S, output Y); MUX2  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule
 module  \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 98dfef9bf..c8475b28f 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -62,6 +62,8 @@ module DFFR (output reg Q, input D, CLK, RESET);
 	end
 endmodule // DFFR (positive clock edge; synchronous reset)
 
+// TODO add more DFF sim cells
+
 module VCC(output V);
 	assign V = 1;
 endmodule
-- 
cgit v1.2.3


From 1b9f7f49b5e90f51f8c3c2d2e8afbaa074137413 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Fri, 6 Sep 2019 09:01:07 +0200
Subject: add more DFF to sim lib

---
 techlibs/gowin/cells_map.v |  12 +++---
 techlibs/gowin/cells_sim.v | 105 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 111 insertions(+), 6 deletions(-)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index aea11d97e..08eb0a9c3 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -32,8 +32,8 @@ module  \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D),
 module  \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
 
 // DFFS      D Flip-Flop with Synchronous Set
-module  \$__DFFS_PN1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!S)); endmodule
-module  \$__DFFS_PP1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(S)); endmodule
+module  \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
+module  \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule
 
 // DFFP      D Flip-Flop with Asynchronous Preset
 module  \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
@@ -43,11 +43,11 @@ module  \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q
 module  \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule
 
 // DFFPE     D Flip-Flop with Clock Enable and Asynchronous Preset
-module  \$__DFFE_PP1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
-module  \$__DFFE_PN1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
+module  \$__DFFE_PP1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
+module  \$__DFFE_PN1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
 // DFFCE     D Flip-Flop with Clock Enable and Asynchronous Clear
-module  \$__DFFE_PP0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
-module  \$__DFFE_PN0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
+module  \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
+module  \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
 
 
 module  \$_MUX_ (input A, B, S, output Y); MUX2  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index c8475b28f..a2f60b99e 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -62,6 +62,111 @@ module DFFR (output reg Q, input D, CLK, RESET);
 	end
 endmodule // DFFR (positive clock edge; synchronous reset)
 
+module DFFE (output reg Q, input D, CLK, CE);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (CE)
+      Q <= D;
+  end
+endmodule // DFFE (positive clock edge; clock enable)
+
+
+module DFFS (output reg Q, input D, CLK, SET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (SET)
+      Q <= 1'b1;
+    else
+      Q <= D;	
+  end
+endmodule // DFFS (positive clock edge; synchronous set)
+
+
+module DFFSE (output reg Q, input D, CLK, CE, SET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (SET)
+      Q <= 1'b1;
+    else if (CE)
+      Q <= D;
+end
+endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
+
+
+module DFFR (output reg Q, input D, CLK, RESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (RESET)
+      Q <= 1'b0;
+    else
+      Q <= D;
+  end
+endmodule // DFFR (positive clock edge; synchronous reset)
+
+
+module DFFRE (output reg Q, input D, CLK, CE, RESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK) begin
+    if (RESET)
+      Q <= 1'b0;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
+
+
+module DFFP (output reg Q, input D, CLK, PRESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK or posedge PRESET) begin
+    if(PRESET)
+      Q <= 1'b1;
+    else
+      Q <= D;
+  end
+endmodule // DFFP (positive clock edge; asynchronous preset)
+
+
+module DFFPE (output reg Q, input D, CLK, CE, PRESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK or posedge PRESET) begin
+    if(PRESET)
+      Q <= 1'b1;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
+
+
+module DFFC (output reg Q, input D, CLK, CLEAR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK or posedge CLEAR) begin
+    if(CLEAR)
+      Q <= 1'b0;
+    else
+      Q <= D;
+  end
+endmodule // DFFC (positive clock edge; asynchronous clear)
+
+
+module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(posedge CLK or posedge CLEAR) begin
+    if(CLEAR)
+      Q <= 1'b0;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
+
 // TODO add more DFF sim cells
 
 module VCC(output V);
-- 
cgit v1.2.3


From 96efa63f16ae30927759b374c86a68753199d0d2 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Fri, 6 Sep 2019 10:55:04 +0200
Subject: fix BRAM width and init

---
 techlibs/gowin/brams_map.v    | 38 +++++++++++++++++++++++++++-----------
 techlibs/gowin/synth_gowin.cc |  2 +-
 2 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v
index c60330b4f..6c5e4733a 100644
--- a/techlibs/gowin/brams_map.v
+++ b/techlibs/gowin/brams_map.v
@@ -8,23 +8,24 @@
 module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter CFG_ABITS = 10;
 	parameter CFG_DBITS = 16;
-	parameter CFG_ENABLE_A = 3;
-
-        parameter [16383:0] INIT = 16384'hx;
-        parameter CLKPOL2 = 1;
-        parameter CLKPOL3 = 1;
+	parameter CFG_ENABLE_A = 1;
+	parameter [16383:0] INIT = 16384'hx;
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
 
 	input CLK2;
 	input CLK3;
 
 	input [CFG_ABITS-1:0] A1ADDR;
 	input [CFG_DBITS-1:0] A1DATA;   
-        input [CFG_ENABLE_A-1:0] A1EN;
+	input [CFG_ENABLE_A-1:0] A1EN;
 
 	input [CFG_ABITS-1:0] B1ADDR;
 	output [CFG_DBITS-1:0] B1DATA;
 	input B1EN;
 
+	wire [31-CFG_DBITS:0] open;
+
 	
 	generate if (CFG_DBITS == 1) begin
 		SDP   #(
@@ -39,7 +40,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
 			.WREB(1'b0),   .CEB(B1EN),
 			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-			.DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+			.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+			.DO({open, B1DATA}),
+			.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
+			.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 		);
 	end else if (CFG_DBITS == 2) begin
 		SDP    #(
@@ -54,7 +58,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
 			.WREB(1'b0),   .CEB(B1EN),
 			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+			.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+			.DO({open, B1DATA}),
+			.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
+			.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 		);
 	end else if (CFG_DBITS <= 4) begin
 		SDP    #(
@@ -69,7 +76,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.WREA(A1EN),   .OCE(1'b0),
 			.WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
 			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+			.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+			.DO({open, B1DATA}),
+			.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
+			.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 		);
 	end else if (CFG_DBITS <= 8) begin
 		SDP    #(
@@ -84,7 +94,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
 			.WREB(1'b0),   .CEB(B1EN),
 			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+			.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+			.DO({open, B1DATA}),
+			.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
+			.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 		);
 	end else if (CFG_DBITS <= 16) begin
 		SDP    #(
@@ -99,7 +112,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.WREA(A1EN),   .OCE(1'b0),
 			.WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
 			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+			.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+			.DO({open, B1DATA}),
+			.ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, 2'b11}),
+			.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 		);
 	end else begin
 		wire TECHMAP_FAIL = 1'b1;
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index cfddcec12..f67627e8a 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -211,7 +211,7 @@ struct SynthGowinPass : public ScriptPass
 		if (check_label("map_cells"))
 		{
 			run("techmap -map +/gowin/cells_map.v");
-			run("setundef -undriven -zero");
+			run("setundef -undriven -params -zero");
 			run("hilomap -singleton -hicell VCC V -locell GND G");
 			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
 			run("dffinit  -ff DFF Q INIT");
-- 
cgit v1.2.3


From 2fb20f184aad4e0286afb6b44712cf5bffb531f4 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Fri, 6 Sep 2019 11:28:17 +0200
Subject: Revert "add MUX support"

It turns out that they make everything worse and they don't PnR.

This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
---
 techlibs/gowin/cells_map.v    |  3 ---
 techlibs/gowin/cells_sim.v    | 13 -------------
 techlibs/gowin/synth_gowin.cc |  1 -
 3 files changed, 17 deletions(-)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 08eb0a9c3..dc0e16db8 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -50,9 +50,6 @@ module  \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D
 module  \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
 
 
-module  \$_MUX_ (input A, B, S, output Y); MUX2  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule
-module  \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule
-
 module \$lut (A, Y);
   parameter WIDTH = 0;
   parameter LUT = 0;
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index a2f60b99e..b70d1299c 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -24,19 +24,6 @@ module LUT4(output F, input I0, I1, I2, I3);
 	assign F = I0 ? s1[1] : s1[0];
 endmodule
 
-module MUX2 (I0, I1, S0, O);
-input I0, I1, S0;
-output O;
-assign O = S0 ? I1 : I0;
-endmodule
-
-module MUX4 (I0, I1, I2, I3, S0, S1, O);
-input I0, I1, I2, I3, S0, S1;
-output O;
-assign O = S1 ? (S0 ? I3 : I2) :
-                (S0 ? I1 : I0);
-endmodule
-
 module DFF (output reg Q, input CLK, D);
 	parameter [0:0] INIT = 1'b0;
 	initial Q = INIT;
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index f67627e8a..e93225fab 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -196,7 +196,6 @@ struct SynthGowinPass : public ScriptPass
 			run("opt_clean");
 			if (!nodffe)
 				run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
-			run("muxcover -mux4");
 			run("techmap -map +/gowin/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
-- 
cgit v1.2.3


From 72323e11a4ee222c0ce928669d33333c46fb25aa Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 16 Oct 2019 11:24:56 +0200
Subject: remove duplicate DFFR

---
 techlibs/gowin/cells_sim.v | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index b70d1299c..de0cfa9f3 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -38,16 +38,6 @@ module DFFN (output reg Q, input CLK, D);
 		Q <= D;
 endmodule
 
-module DFFR (output reg Q, input D, CLK, RESET);
-	parameter [0:0] INIT = 1'b0;
-	initial Q = INIT;
-	always @(posedge CLK) begin
-        if (RESET)
-                Q <= 1'b0;
-        else
-                Q <= D;
-	end
-endmodule // DFFR (positive clock edge; synchronous reset)
 
 module DFFE (output reg Q, input D, CLK, CE);
   parameter [0:0] INIT = 1'b0;
-- 
cgit v1.2.3


From af7bdd598e017b0e8887d893c901ae93935d20b2 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 21 Oct 2019 12:00:27 +0200
Subject: use ADDSUB ALU mode to remove inverters

---
 techlibs/gowin/arith_map.v |  6 ++--
 techlibs/gowin/cells_sim.v | 78 +++++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 77 insertions(+), 7 deletions(-)

diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
index af805b254..b6f9e8c38 100644
--- a/techlibs/gowin/arith_map.v
+++ b/techlibs/gowin/arith_map.v
@@ -40,15 +40,15 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
    \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
    wire [Y_WIDTH-1:0] 	AA = A_buf;
-   wire [Y_WIDTH-1:0] 	BB = BI ? ~B_buf : B_buf;
+   wire [Y_WIDTH-1:0] 	BB = B_buf;
    wire [Y_WIDTH-1:0] 	C = {CO, CI};
 
    genvar 		i;
    generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-      ALU #(.ALU_MODE(0))
+      ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub
       alu(.I0(AA[i]),
 	  .I1(BB[i]),
-	  .I3(1'b0),
+	  .I3(~BI),
 	  .CIN(C[i]),
 	  .COUT(CO[i]),
 	  .SUM(Y[i])
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index de0cfa9f3..a392f5580 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -166,10 +166,80 @@ module GSR (input GSRI);
 	wire GSRO = GSRI;
 endmodule
 
-module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
-   parameter [3:0] ALU_MODE = 0; // default 0 = ADD
-   assign  {COUT, SUM} = CIN + I1 + I0;
-endmodule // alu
+module ALU (SUM, COUT, I0, I1, I3, CIN);
+
+input I0;
+input I1;
+input I3;
+input CIN;
+output SUM;
+output COUT;
+
+parameter ADD = 0;
+parameter SUB = 1;
+parameter ADDSUB = 2;
+parameter NE = 3;
+parameter GE = 4;
+parameter LE = 5;
+parameter CUP = 6;
+parameter CDN = 7;
+parameter CUPCDN = 8;
+parameter MULT = 9;
+
+parameter ALU_MODE = 0;
+
+reg S, C;
+
+assign SUM = S ^ CIN;
+assign COUT = S? CIN : C;
+
+always @(I0, I1, I3,CIN) begin
+	case (ALU_MODE)
+		ADD: begin
+			S = I0 ^ I1;
+			C = I0;
+		end
+		SUB: begin
+			S = I0 ^ ~I1;
+			C = I0;
+		end
+		ADDSUB: begin
+			S = I3? I0 ^ I1 : I0 ^ ~I1;
+			C = I0;
+		end
+		NE: begin
+			S = I0 ^ ~I1;
+			C = 1'b1;
+		end
+		GE: begin
+			S = I0 ^ ~I1;
+			C = I0;
+		end
+		LE: begin
+			S = ~I0 ^ I1;
+			C = I1;
+		end
+		CUP: begin
+			S = I0;
+			C = 1'b0;
+		end
+		CDN: begin
+			S = ~I0;
+			C = 1'b1;
+		end
+		CUPCDN: begin
+			S = I3? I0 : ~I0;
+			C = I0;
+		end
+		MULT: begin
+			S = I0 & I1;
+			C = I0 & I1;
+		end
+	endcase
+end
+
+endmodule
+
 
 module RAM16S4 (DO, DI, AD, WRE, CLK);
    parameter WIDTH  = 4;
-- 
cgit v1.2.3


From 8a2699c40c9b60d28ab69c1e87629b467ccc9890 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 21 Oct 2019 12:31:11 +0200
Subject: add negedge DFF

---
 techlibs/gowin/cells_map.v |  33 ++++++++++---
 techlibs/gowin/cells_sim.v | 121 ++++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 139 insertions(+), 15 deletions(-)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index dc0e16db8..e485feebd 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -3,15 +3,8 @@
 // DFFSE     D Flip-Flop with Clock Enable and Synchronous Set
 // DFFRE     D Flip-Flop with Clock Enable and Synchronous Reset
 
-// DFFNS     D Flip-Flop with Negative-Edge Clock and Synchronous Set
 // DFFNSE    D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
-// DFFNR     D Flip-Flop with Negative-Edge Clock and Synchronous Reset
 // DFFNRE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
-// DFFNP     D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
-// DFFNPE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
-// DFFNC     D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
-// DFFNCE    D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
-
 //TODO all DFF* have INIT
 
 // DFFN      D Flip-Flop with Negative-Edge Clock
@@ -31,24 +24,50 @@ module  \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .
 module  \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
 module  \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
 
+// DFFNR     D Flip-Flop with Negative-Edge Clock and Synchronous Reset
+module  \$__DFFS_NN0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
+module  \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
+
 // DFFS      D Flip-Flop with Synchronous Set
 module  \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
 module  \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule
 
+// DFFNS     D Flip-Flop with Negative-Edge Clock and Synchronous Set
+module  \$__DFFS_NN1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
+module  \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule
+
 // DFFP      D Flip-Flop with Asynchronous Preset
 module  \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
 module  \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule
+
+// DFFNP     D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
+module  \$_DFF_NP1_ (input D, C, R, output Q); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule
+
 // DFFC      D Flip-Flop with Asynchronous Clear
 module  \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule
 module  \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule
 
+// DFFNC     D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
+module  \$_DFF_NP0_ (input D, C, R, output Q); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule
+
 // DFFPE     D Flip-Flop with Clock Enable and Asynchronous Preset
 module  \$__DFFE_PP1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
 module  \$__DFFE_PN1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
+
+// DFFNPE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
+module  \$__DFFE_NP1 (input D, C, R, E, output Q); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
+module  \$__DFFE_NN1 (input D, C, R, E, output Q); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
+
 // DFFCE     D Flip-Flop with Clock Enable and Asynchronous Clear
 module  \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
 module  \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
 
+// DFFNCE    D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
+module  \$__DFFE_NP0 (input D, C, R, E, output Q); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
+module  \$__DFFE_NN0 (input D, C, R, E, output Q); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
+
 
 module \$lut (A, Y);
   parameter WIDTH = 0;
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index a392f5580..8280982d6 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -31,14 +31,6 @@ module DFF (output reg Q, input CLK, D);
 		Q <= D;
 endmodule
 
-module DFFN (output reg Q, input CLK, D);
-	parameter [0:0] INIT = 1'b0;
-	initial Q = INIT;
-	always @(negedge CLK)
-		Q <= D;
-endmodule
-
-
 module DFFE (output reg Q, input D, CLK, CE);
   parameter [0:0] INIT = 1'b0;
   initial Q = INIT;
@@ -144,6 +136,119 @@ module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
   end
 endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
 
+
+module DFFN (output reg Q, input CLK, D);
+	parameter [0:0] INIT = 1'b0;
+	initial Q = INIT;
+	always @(negedge CLK)
+		Q <= D;
+endmodule
+
+module DFFNE (output reg Q, input D, CLK, CE);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (CE)
+      Q <= D;
+  end
+endmodule // DFFNE (negative clock edge; clock enable)
+
+
+module DFFNS (output reg Q, input D, CLK, SET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (SET)
+      Q <= 1'b1;
+    else
+      Q <= D;	
+  end
+endmodule // DFFNS (negative clock edge; synchronous set)
+
+
+module DFFNSE (output reg Q, input D, CLK, CE, SET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (SET)
+      Q <= 1'b1;
+    else if (CE)
+      Q <= D;
+end
+endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
+
+
+module DFFNR (output reg Q, input D, CLK, RESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (RESET)
+      Q <= 1'b0;
+    else
+      Q <= D;
+  end
+endmodule // DFFNR (negative clock edge; synchronous reset)
+
+
+module DFFNRE (output reg Q, input D, CLK, CE, RESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK) begin
+    if (RESET)
+      Q <= 1'b0;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
+
+
+module DFFNP (output reg Q, input D, CLK, PRESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK or posedge PRESET) begin
+    if(PRESET)
+      Q <= 1'b1;
+    else
+      Q <= D;
+  end
+endmodule // DFFNP (negative clock edge; asynchronous preset)
+
+
+module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK or posedge PRESET) begin
+    if(PRESET)
+      Q <= 1'b1;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
+
+
+module DFFNC (output reg Q, input D, CLK, CLEAR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK or posedge CLEAR) begin
+    if(CLEAR)
+      Q <= 1'b0;
+    else
+      Q <= D;
+  end
+endmodule // DFFNC (negative clock edge; asynchronous clear)
+
+
+module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q = INIT;
+  always @(negedge CLK or posedge CLEAR) begin
+    if(CLEAR)
+      Q <= 1'b0;
+    else if (CE)
+      Q <= D;
+  end
+endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
+
 // TODO add more DFF sim cells
 
 module VCC(output V);
-- 
cgit v1.2.3


From 03457ee13e36574add688a9c2c5c0641a4d6df05 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 21 Oct 2019 16:08:13 +0200
Subject: add a few more missing dff

---
 techlibs/gowin/cells_map.v | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index e485feebd..425cf7f59 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -1,10 +1,3 @@
-// TODO add these DFF types
-// Primitive Description
-// DFFSE     D Flip-Flop with Clock Enable and Synchronous Set
-// DFFRE     D Flip-Flop with Clock Enable and Synchronous Reset
-
-// DFFNSE    D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
-// DFFNRE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
 //TODO all DFF* have INIT
 
 // DFFN      D Flip-Flop with Negative-Edge Clock
@@ -28,6 +21,14 @@ module  \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D),
 module  \$__DFFS_NN0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
 module  \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
 
+// DFFRE     D Flip-Flop with Clock Enable and Synchronous Reset
+module  \$__DFFSE_PN0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule
+module  \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule
+
+// DFFNRE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
+module  \$__DFFNSE_PN0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule
+module  \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule
+
 // DFFS      D Flip-Flop with Synchronous Set
 module  \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
 module  \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule
@@ -36,6 +37,14 @@ module  \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D),
 module  \$__DFFS_NN1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
 module  \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule
 
+// DFFSE     D Flip-Flop with Clock Enable and Synchronous Set
+module  \$__DFFSE_PN1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule
+module  \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule
+
+// DFFNSE    D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
+module  \$__DFFSE_NN1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule
+module  \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule
+
 // DFFP      D Flip-Flop with Asynchronous Preset
 module  \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
 module  \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule
-- 
cgit v1.2.3


From 83fbfe0964dc7315ca6d508e6069507250d9f093 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 21 Oct 2019 16:25:15 +0200
Subject: Add some tests

Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
---
 tests/arch/gowin/.gitignore  |  3 +++
 tests/arch/gowin/add_sub.ys  | 13 +++++++++++
 tests/arch/gowin/adffs.ys    | 55 ++++++++++++++++++++++++++++++++++++++++++++
 tests/arch/gowin/counter.ys  | 15 ++++++++++++
 tests/arch/gowin/dffs.ys     | 25 ++++++++++++++++++++
 tests/arch/gowin/logic.ys    | 13 +++++++++++
 tests/arch/gowin/memory.ys   | 18 +++++++++++++++
 tests/arch/gowin/mux.ys      | 50 ++++++++++++++++++++++++++++++++++++++++
 tests/arch/gowin/run-test.sh | 20 ++++++++++++++++
 tests/arch/gowin/shifter.ys  | 12 ++++++++++
 10 files changed, 224 insertions(+)
 create mode 100644 tests/arch/gowin/.gitignore
 create mode 100644 tests/arch/gowin/add_sub.ys
 create mode 100644 tests/arch/gowin/adffs.ys
 create mode 100644 tests/arch/gowin/counter.ys
 create mode 100644 tests/arch/gowin/dffs.ys
 create mode 100644 tests/arch/gowin/logic.ys
 create mode 100644 tests/arch/gowin/memory.ys
 create mode 100644 tests/arch/gowin/mux.ys
 create mode 100755 tests/arch/gowin/run-test.sh
 create mode 100644 tests/arch/gowin/shifter.ys

diff --git a/tests/arch/gowin/.gitignore b/tests/arch/gowin/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/arch/gowin/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/arch/gowin/add_sub.ys b/tests/arch/gowin/add_sub.ys
new file mode 100644
index 000000000..9b53dc0a9
--- /dev/null
+++ b/tests/arch/gowin/add_sub.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:ALU
+select -assert-count 8 t:OBUF
+select -assert-count 8 t:IBUF
+select -assert-count 1 t:GND
+select -assert-count 1 t:VCC
+select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D
+
diff --git a/tests/arch/gowin/adffs.ys b/tests/arch/gowin/adffs.ys
new file mode 100644
index 000000000..fc7ee01f2
--- /dev/null
+++ b/tests/arch/gowin/adffs.ys
@@ -0,0 +1,55 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+stat
+select -assert-count 1 t:DFFC
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFC
+select -assert-count 1 t:LUT1
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFS
+select -assert-count 4 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFNR
+select -assert-count 1 t:LUT1
+select -assert-count 4 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D
diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys
new file mode 100644
index 000000000..920479d44
--- /dev/null
+++ b/tests/arch/gowin/counter.ys
@@ -0,0 +1,15 @@
+read_verilog ../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8 t:DFFC
+select -assert-count 8 t:ALU
+select -assert-count 1 t:GND
+select -assert-count 1 t:VCC
+select -assert-count 2 t:IBUF
+select -assert-count 8 t:OBUF
+select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/dffs.ys b/tests/arch/gowin/dffs.ys
new file mode 100644
index 000000000..9c012213f
--- /dev/null
+++ b/tests/arch/gowin/dffs.ys
@@ -0,0 +1,25 @@
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFF
+select -assert-count 2 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFE
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFE t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/logic.ys b/tests/arch/gowin/logic.ys
new file mode 100644
index 000000000..d2b9e4540
--- /dev/null
+++ b/tests/arch/gowin/logic.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:LUT1
+select -assert-count 6 t:LUT2
+select -assert-count 2 t:LUT4
+select -assert-count 8 t:IBUF
+select -assert-count 10 t:OBUF
+select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/memory.ys
new file mode 100644
index 000000000..8f88cdd7c
--- /dev/null
+++ b/tests/arch/gowin/memory.ys
@@ -0,0 +1,18 @@
+read_verilog ../common/memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#ERROR: Called with -verify and proof did fail!
+#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 8 t:RAM16S4
+# other logic present that is not simple
+#select -assert-none t:RAM16S4 %% t:* %D
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
new file mode 100644
index 000000000..c9c85019b
--- /dev/null
+++ b/tests/arch/gowin/mux.ys
@@ -0,0 +1,50 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 2 t:LUT4
+select -assert-count 6 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 5 t:LUT4
+select -assert-count 11 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 9 t:LUT4
+select -assert-count 3 t:LUT3
+select -assert-count 20 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/run-test.sh b/tests/arch/gowin/run-test.sh
new file mode 100755
index 000000000..bf19b887d
--- /dev/null
+++ b/tests/arch/gowin/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/arch/gowin/shifter.ys b/tests/arch/gowin/shifter.ys
new file mode 100644
index 000000000..b43b1e869
--- /dev/null
+++ b/tests/arch/gowin/shifter.ys
@@ -0,0 +1,12 @@
+read_verilog ../common/shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8  t:DFF
+select -assert-count 2  t:IBUF
+select -assert-count 8  t:OBUF
+select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D
-- 
cgit v1.2.3


From 8226f2db0b65dffb59c4420de96dccd2e0be36ed Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Thu, 24 Oct 2019 13:39:43 +0200
Subject: ALU sim tweaks

---
 techlibs/gowin/cells_sim.v | 22 +++++++++++-----------
 tests/arch/gowin/mux.ys    |  4 ++--
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 8280982d6..9dac2c2c2 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -280,16 +280,16 @@ input CIN;
 output SUM;
 output COUT;
 
-parameter ADD = 0;
-parameter SUB = 1;
-parameter ADDSUB = 2;
-parameter NE = 3;
-parameter GE = 4;
-parameter LE = 5;
-parameter CUP = 6;
-parameter CDN = 7;
-parameter CUPCDN = 8;
-parameter MULT = 9;
+localparam ADD = 0;
+localparam SUB = 1;
+localparam ADDSUB = 2;
+localparam NE = 3;
+localparam GE = 4;
+localparam LE = 5;
+localparam CUP = 6;
+localparam CDN = 7;
+localparam CUPCDN = 8;
+localparam MULT = 9;
 
 parameter ALU_MODE = 0;
 
@@ -298,7 +298,7 @@ reg S, C;
 assign SUM = S ^ CIN;
 assign COUT = S? CIN : C;
 
-always @(I0, I1, I3,CIN) begin
+always @* begin
 	case (ALU_MODE)
 		ADD: begin
 			S = I0 ^ I1;
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index c9c85019b..d612e4eaa 100644
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -42,8 +42,8 @@ proc
 equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 9 t:LUT4
-select -assert-count 3 t:LUT3
+select -assert-count 10 t:LUT4
+select -assert-count 1 t:LUT3
 select -assert-count 20 t:IBUF
 select -assert-count 1 t:OBUF
 
-- 
cgit v1.2.3


From 5fad53b504a7ac05fb959f0ca84829bd550aac47 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 10:33:27 +0100
Subject: add 32-bit BRAM and byte-enables

---
 techlibs/gowin/bram.txt    |  7 +++++--
 techlibs/gowin/brams_map.v | 22 ++++++++++++++++++++--
 2 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/techlibs/gowin/bram.txt b/techlibs/gowin/bram.txt
index 366a7106e..e406f9c51 100644
--- a/techlibs/gowin/bram.txt
+++ b/techlibs/gowin/bram.txt
@@ -1,5 +1,7 @@
 bram $__GW1NR_SDP
   init 1
+  abits 9 @a9d36
+  dbits 32 @a9d36
   abits 10 @a10d18
   dbits 16 @a10d18
   abits 11 @a11d9
@@ -13,7 +15,8 @@ bram $__GW1NR_SDP
   groups 2
   ports  1 1
   wrmode 1 0
-  enable 1 1 @a10d18
+  enable 4 1 @a9d36
+  enable 2 1 @a10d18
   enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
   transp 0 0
   clocks 2 3
@@ -23,6 +26,6 @@ endbram
 match $__GW1NR_SDP
   min bits 2048
   min efficiency 5
-  shuffle_enable B
+  shuffle_enable A
   make_transp
 endmatch
diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v
index 6c5e4733a..fbebc4af8 100644
--- a/techlibs/gowin/brams_map.v
+++ b/techlibs/gowin/brams_map.v
@@ -109,12 +109,30 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.RESET_MODE("SYNC")
 		) _TECHMAP_REPLACE_ (
 			.CLKA(CLK2),   .CLKB(CLK3),
-			.WREA(A1EN),   .OCE(1'b0),
+			.WREA(|A1EN),   .OCE(1'b0),
 			.WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
 			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
 			.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
 			.DO({open, B1DATA}),
-			.ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, 2'b11}),
+			.ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, A1EN}),
+			.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
+		);
+	end else if (CFG_DBITS <= 32) begin
+		SDP    #(
+      `include "bram_init_16.vh"
+			.READ_MODE(0),
+			.BIT_WIDTH_0(32),
+			.BIT_WIDTH_1(32),
+			.BLK_SEL(3'b000),
+			.RESET_MODE("SYNC")
+		) _TECHMAP_REPLACE_ (
+			.CLKA(CLK2),   .CLKB(CLK3),
+			.WREA(|A1EN),   .OCE(1'b0),
+			.WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
+			.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
+			.DI(A1DATA),
+			.DO(B1DATA),
+			.ADA({A1ADDR, {(10-CFG_ABITS){1'b0}}, A1EN}),
 			.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 		);
 	end else begin
-- 
cgit v1.2.3


From f88335a8a5284a8e69230ec20eeeca6c02b055bf Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 12:49:08 +0100
Subject: add wide luts

---
 techlibs/gowin/cells_map.v    | 24 +++++++++++
 techlibs/gowin/cells_sim.v    | 35 ++++++++++++++++
 techlibs/gowin/synth_gowin.cc | 96 +++++++++++++++++++++++++++----------------
 3 files changed, 119 insertions(+), 36 deletions(-)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 425cf7f59..62cb080d9 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -101,6 +101,30 @@ module \$lut (A, Y);
     if (WIDTH == 4) begin
       LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
         .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+    end else
+    if (WIDTH == 5) begin
+      wire f0, f1;
+      \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0));
+      \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1));
+      MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+    end else
+    if (WIDTH == 6) begin
+      wire f0, f1;
+      \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0));
+      \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1));
+      MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+    end else
+    if (WIDTH == 7) begin
+      wire f0, f1;
+      \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0));
+      \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1));
+      MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+    end else
+    if (WIDTH == 8) begin
+      wire f0, f1;
+      \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0));
+      \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1));
+      MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 9dac2c2c2..0fe2c8c52 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -24,6 +24,41 @@ module LUT4(output F, input I0, I1, I2, I3);
 	assign F = I0 ? s1[1] : s1[0];
 endmodule
 
+module MUX2 (O, I0, I1, S0);
+  input I0,I1;
+  input S0;
+  output O;
+  assign O = S0 ? I1 : I0;
+endmodule
+
+module MUX2_LUT5 (O, I0, I1, S0);
+  input I0,I1;
+  input S0;
+  output O;
+  MUX2 mux2_lut5 (O, I0, I1, S0);
+endmodule
+
+module MUX2_LUT6 (O, I0, I1, S0);
+  input I0,I1;
+  input S0;
+  output O;
+  MUX2 mux2_lut6 (O, I0, I1, S0);
+endmodule
+
+module MUX2_LUT7 (O, I0, I1, S0);
+  input I0,I1;
+  input S0;
+  output O;
+  MUX2 mux2_lut7 (O, I0, I1, S0);
+endmodule
+
+module MUX2_LUT8 (O, I0, I1, S0);
+  input I0,I1;
+  input S0;
+  output O;
+  MUX2 mux2_lut8 (O, I0, I1, S0);
+endmodule
+
 module DFF (output reg Q, input CLK, D);
 	parameter [0:0] INIT = 1'b0;
 	initial Q = INIT;
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index e93225fab..89cbc50ab 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -1,19 +1,19 @@
 /*
- *  yosys -- Yosys Open SYnthesis Suite
+ *	yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *	Copyright (C) 2012	Clifford Wolf <clifford@clifford.at>
  *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
+ *	Permission to use, copy, modify, and/or distribute this software for any
+ *	purpose with or without fee is hereby granted, provided that the above
+ *	copyright notice and this permission notice appear in all copies.
  *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *	THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *	WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *	MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *	ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *	WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *	ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *	OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
 
@@ -31,38 +31,44 @@ struct SynthGowinPass : public ScriptPass
 
 	void help() YS_OVERRIDE
 	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		//	 |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    synth_gowin [options]\n");
+		log("	 synth_gowin [options]\n");
 		log("\n");
 		log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
 		log("\n");
-		log("    -top <module>\n");
-		log("        use the specified module as top module (default='top')\n");
+		log("	 -top <module>\n");
+		log("		 use the specified module as top module (default='top')\n");
 		log("\n");
-		log("    -vout <file>\n");
-		log("        write the design to the specified Verilog netlist file. writing of an\n");
-		log("        output file is omitted if this parameter is not specified.\n");
+		log("	 -vout <file>\n");
+		log("		 write the design to the specified Verilog netlist file. writing of an\n");
+		log("		 output file is omitted if this parameter is not specified.\n");
 		log("\n");
-		log("    -run <from_label>:<to_label>\n");
-		log("        only run the commands between the labels (see below). an empty\n");
-		log("        from label is synonymous to 'begin', and empty to label is\n");
-		log("        synonymous to the end of the command list.\n");
+		log("	 -run <from_label>:<to_label>\n");
+		log("		 only run the commands between the labels (see below). an empty\n");
+		log("		 from label is synonymous to 'begin', and empty to label is\n");
+		log("		 synonymous to the end of the command list.\n");
 		log("\n");
-		log("    -nodffe\n");
-		log("        do not use flipflops with CE in output netlist\n");
+		log("	 -nodffe\n");
+		log("		 do not use flipflops with CE in output netlist\n");
 		log("\n");
-		log("    -nobram\n");
-		log("        do not use BRAM cells in output netlist\n");
+		log("	 -nobram\n");
+		log("		 do not use BRAM cells in output netlist\n");
 		log("\n");
-		log("    -nodram\n");
-		log("        do not use distributed RAM cells in output netlist\n");
+		log("	 -nodram\n");
+		log("		 do not use distributed RAM cells in output netlist\n");
 		log("\n");
-		log("    -noflatten\n");
-		log("        do not flatten design before synthesis\n");
+		log("	 -noflatten\n");
+		log("		 do not flatten design before synthesis\n");
 		log("\n");
-		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("	 -retime\n");
+		log("		 run 'abc' with -dff option\n");
+		log("\n");
+		log("	 -nowidelut\n");
+		log("		 do not use muxes to implement LUTs larger than LUT4s\n");
+		log("\n");
+		log("	 -abc9\n");
+		log("		 use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -71,7 +77,7 @@ struct SynthGowinPass : public ScriptPass
 	}
 
 	string top_opt, vout_file;
-	bool retime, nobram, nodram, flatten, nodffe;
+	bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -82,6 +88,8 @@ struct SynthGowinPass : public ScriptPass
 		nobram = false;
 		nodffe = false;
 		nodram = false;
+		nowidelut = false;
+		abc9 = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -128,6 +136,14 @@ struct SynthGowinPass : public ScriptPass
 				flatten = false;
 				continue;
 			}
+			if (args[argidx] == "-nowidelut") {
+				nowidelut = true;
+				continue;
+			}
+			if (args[argidx] == "-abc9") {
+				abc9 = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -164,7 +180,7 @@ struct SynthGowinPass : public ScriptPass
 			run("synth -run coarse");
 		}
 		
-                if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/gowin/bram.txt");
 			run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
@@ -203,7 +219,15 @@ struct SynthGowinPass : public ScriptPass
 
 		if (check_label("map_luts"))
 		{
-			run("abc -lut 4");
+			if (nowidelut && abc9) {
+				run("abc9 -lut 4");
+			} else if (nowidelut && !abc9) {
+				run("abc -lut 4");
+			} else if (!nowidelut && abc9) {
+				run("abc9 -lut 4:8");
+			} else if (!nowidelut && !abc9) {
+				run("abc -lut 4:8");
+			}
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From 293b2c2de5c127d860d9ce0c7ac98908fa053520 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 12:57:12 +0100
Subject: undo formatting fuckup

---
 techlibs/gowin/synth_gowin.cc | 50 +++++++++++++++++++++----------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 89cbc50ab..a44bbe2f6 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -33,42 +33,42 @@ struct SynthGowinPass : public ScriptPass
 	{
 		//	 |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("	 synth_gowin [options]\n");
+		log("		 synth_gowin [options]\n");
 		log("\n");
 		log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
 		log("\n");
-		log("	 -top <module>\n");
-		log("		 use the specified module as top module (default='top')\n");
+		log("		 -top <module>\n");
+		log("				 use the specified module as top module (default='top')\n");
 		log("\n");
-		log("	 -vout <file>\n");
-		log("		 write the design to the specified Verilog netlist file. writing of an\n");
-		log("		 output file is omitted if this parameter is not specified.\n");
+		log("		 -vout <file>\n");
+		log("				 write the design to the specified Verilog netlist file. writing of an\n");
+		log("				 output file is omitted if this parameter is not specified.\n");
 		log("\n");
-		log("	 -run <from_label>:<to_label>\n");
-		log("		 only run the commands between the labels (see below). an empty\n");
-		log("		 from label is synonymous to 'begin', and empty to label is\n");
-		log("		 synonymous to the end of the command list.\n");
+		log("		 -run <from_label>:<to_label>\n");
+		log("				 only run the commands between the labels (see below). an empty\n");
+		log("				 from label is synonymous to 'begin', and empty to label is\n");
+		log("				 synonymous to the end of the command list.\n");
 		log("\n");
-		log("	 -nodffe\n");
-		log("		 do not use flipflops with CE in output netlist\n");
+		log("		 -nodffe\n");
+		log("				 do not use flipflops with CE in output netlist\n");
 		log("\n");
-		log("	 -nobram\n");
-		log("		 do not use BRAM cells in output netlist\n");
+		log("		 -nobram\n");
+		log("				 do not use BRAM cells in output netlist\n");
 		log("\n");
-		log("	 -nodram\n");
-		log("		 do not use distributed RAM cells in output netlist\n");
+		log("		 -nodram\n");
+		log("				 do not use distributed RAM cells in output netlist\n");
 		log("\n");
-		log("	 -noflatten\n");
-		log("		 do not flatten design before synthesis\n");
+		log("		 -noflatten\n");
+		log("				 do not flatten design before synthesis\n");
 		log("\n");
-		log("	 -retime\n");
-		log("		 run 'abc' with -dff option\n");
+		log("		 -retime\n");
+		log("				 run 'abc' with -dff option\n");
 		log("\n");
-		log("	 -nowidelut\n");
-		log("		 do not use muxes to implement LUTs larger than LUT4s\n");
+		log("		 -nowidelut\n");
+		log("				 do not use muxes to implement LUTs larger than LUT4s\n");
 		log("\n");
-		log("	 -abc9\n");
-		log("		 use new ABC9 flow (EXPERIMENTAL)\n");
+		log("		 -abc9\n");
+		log("				 use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -237,7 +237,7 @@ struct SynthGowinPass : public ScriptPass
 			run("setundef -undriven -params -zero");
 			run("hilomap -singleton -hicell VCC V -locell GND G");
 			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
-			run("dffinit  -ff DFF Q INIT");
+			run("dffinit	-ff DFF Q INIT");
 			run("clean");
 
 		}
-- 
cgit v1.2.3


From c1921b45619fbca4cbcafe3cd9cfdc0fe29e251c Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 13:01:20 +0100
Subject: really really fix formatting maybe

---
 techlibs/gowin/synth_gowin.cc | 82 +++++++++++++++++++++----------------------
 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index a44bbe2f6..a95d81bfd 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -32,46 +32,46 @@ struct SynthGowinPass : public ScriptPass
 	void help() YS_OVERRIDE
 	{
 		//	 |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("		 synth_gowin [options]\n");
-		log("\n");
-		log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
-		log("\n");
-		log("		 -top <module>\n");
-		log("				 use the specified module as top module (default='top')\n");
-		log("\n");
-		log("		 -vout <file>\n");
-		log("				 write the design to the specified Verilog netlist file. writing of an\n");
-		log("				 output file is omitted if this parameter is not specified.\n");
-		log("\n");
-		log("		 -run <from_label>:<to_label>\n");
-		log("				 only run the commands between the labels (see below). an empty\n");
-		log("				 from label is synonymous to 'begin', and empty to label is\n");
-		log("				 synonymous to the end of the command list.\n");
-		log("\n");
-		log("		 -nodffe\n");
-		log("				 do not use flipflops with CE in output netlist\n");
-		log("\n");
-		log("		 -nobram\n");
-		log("				 do not use BRAM cells in output netlist\n");
-		log("\n");
-		log("		 -nodram\n");
-		log("				 do not use distributed RAM cells in output netlist\n");
-		log("\n");
-		log("		 -noflatten\n");
-		log("				 do not flatten design before synthesis\n");
-		log("\n");
-		log("		 -retime\n");
-		log("				 run 'abc' with -dff option\n");
-		log("\n");
-		log("		 -nowidelut\n");
-		log("				 do not use muxes to implement LUTs larger than LUT4s\n");
-		log("\n");
-		log("		 -abc9\n");
-		log("				 use new ABC9 flow (EXPERIMENTAL)\n");
-		log("\n");
-		log("\n");
-		log("The following commands are executed by this synthesis command:\n");
+    log("\n");
+    log("    synth_gowin [options]\n");
+    log("\n");
+    log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
+    log("\n");
+    log("    -top <module>\n");
+    log("        use the specified module as top module (default='top')\n");
+    log("\n");
+    log("    -vout <file>\n");
+    log("        write the design to the specified Verilog netlist file. writing of an\n");
+    log("        output file is omitted if this parameter is not specified.\n");
+    log("\n");
+    log("    -run <from_label>:<to_label>\n");
+    log("        only run the commands between the labels (see below). an empty\n");
+    log("        from label is synonymous to 'begin', and empty to label is\n");
+    log("        synonymous to the end of the command list.\n");
+    log("\n");
+    log("    -nodffe\n");
+    log("        do not use flipflops with CE in output netlist\n");
+    log("\n");
+    log("    -nobram\n");
+    log("        do not use BRAM cells in output netlist\n");
+    log("\n");
+    log("    -nodram\n");
+    log("        do not use distributed RAM cells in output netlist\n");
+    log("\n");
+    log("    -noflatten\n");
+    log("        do not flatten design before synthesis\n");
+    log("\n");
+    log("    -retime\n");
+    log("        run 'abc' with -dff option\n");
+    log("\n");
+    log("    -nowidelut\n");
+    log("        do not use muxes to implement LUTs larger than LUT4s\n");
+    log("\n");
+    log("    -abc9\n");
+    log("        use new ABC9 flow (EXPERIMENTAL)\n");
+    log("\n");
+    log("\n");
+    log("The following commands are executed by this synthesis command:\n");
 		help_script();
 		log("\n");
 	}
@@ -237,7 +237,7 @@ struct SynthGowinPass : public ScriptPass
 			run("setundef -undriven -params -zero");
 			run("hilomap -singleton -hicell VCC V -locell GND G");
 			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
-			run("dffinit	-ff DFF Q INIT");
+			run("dffinit -ff DFF Q INIT");
 			run("clean");
 
 		}
-- 
cgit v1.2.3


From 2f5e9e9885df0011a3b70b0ab64f54fcd33ce347 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 13:10:12 +0100
Subject: More formatting

---
 techlibs/gowin/synth_gowin.cc | 104 ++++++++++++++++++++----------------------
 1 file changed, 49 insertions(+), 55 deletions(-)

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index a95d81bfd..e9b2ccded 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -1,19 +1,19 @@
 /*
- *	yosys -- Yosys Open SYnthesis Suite
+ *  yosys -- Yosys Open SYnthesis Suite
  *
- *	Copyright (C) 2012	Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
  *
- *	Permission to use, copy, modify, and/or distribute this software for any
- *	purpose with or without fee is hereby granted, provided that the above
- *	copyright notice and this permission notice appear in all copies.
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
  *
- *	THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *	WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *	MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *	ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *	WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *	ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *	OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
 
@@ -31,47 +31,41 @@ struct SynthGowinPass : public ScriptPass
 
 	void help() YS_OVERRIDE
 	{
-		//	 |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-    log("\n");
-    log("    synth_gowin [options]\n");
-    log("\n");
-    log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
-    log("\n");
-    log("    -top <module>\n");
-    log("        use the specified module as top module (default='top')\n");
-    log("\n");
-    log("    -vout <file>\n");
-    log("        write the design to the specified Verilog netlist file. writing of an\n");
-    log("        output file is omitted if this parameter is not specified.\n");
-    log("\n");
-    log("    -run <from_label>:<to_label>\n");
-    log("        only run the commands between the labels (see below). an empty\n");
-    log("        from label is synonymous to 'begin', and empty to label is\n");
-    log("        synonymous to the end of the command list.\n");
-    log("\n");
-    log("    -nodffe\n");
-    log("        do not use flipflops with CE in output netlist\n");
-    log("\n");
-    log("    -nobram\n");
-    log("        do not use BRAM cells in output netlist\n");
-    log("\n");
-    log("    -nodram\n");
-    log("        do not use distributed RAM cells in output netlist\n");
-    log("\n");
-    log("    -noflatten\n");
-    log("        do not flatten design before synthesis\n");
-    log("\n");
-    log("    -retime\n");
-    log("        run 'abc' with -dff option\n");
-    log("\n");
-    log("    -nowidelut\n");
-    log("        do not use muxes to implement LUTs larger than LUT4s\n");
-    log("\n");
-    log("    -abc9\n");
-    log("        use new ABC9 flow (EXPERIMENTAL)\n");
-    log("\n");
-    log("\n");
-    log("The following commands are executed by this synthesis command:\n");
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_gowin [options]\n");
+		log("\n");
+		log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module (default='top')\n");
+		log("\n");
+		log("    -vout <file>\n");
+		log("        write the design to the specified Verilog netlist file. writing of an\n");
+		log("        output file is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -nodffe\n");
+		log("        do not use flipflops with CE in output netlist\n");
+		log("\n");
+		log("    -nobram\n");
+		log("        do not use BRAM cells in output netlist\n");
+		log("\n");
+		log("    -nodram\n");
+		log("        do not use distributed RAM cells in output netlist\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -retime\n");
+		log("        run 'abc' with -dff option\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
 		help_script();
 		log("\n");
 	}
@@ -180,7 +174,7 @@ struct SynthGowinPass : public ScriptPass
 			run("synth -run coarse");
 		}
 		
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+                if (!nobram && check_label("bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/gowin/bram.txt");
 			run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
@@ -237,7 +231,7 @@ struct SynthGowinPass : public ScriptPass
 			run("setundef -undriven -params -zero");
 			run("hilomap -singleton -hicell VCC V -locell GND G");
 			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
-			run("dffinit -ff DFF Q INIT");
+			run("dffinit  -ff DFF Q INIT");
 			run("clean");
 
 		}
-- 
cgit v1.2.3


From 4ec4d5ec7e6c70c50c513de93c1d478ff76d8298 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 14:28:03 +0100
Subject: actually run the gowin tests

---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Makefile b/Makefile
index 845a97b50..6e7681cf3 100644
--- a/Makefile
+++ b/Makefile
@@ -718,6 +718,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/arch/ecp5 && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/efinix && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
-- 
cgit v1.2.3


From 9517525224c7bc4b8ac7d093066485888a337b76 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 14:40:12 +0100
Subject: do not use wide luts in testcase

---
 tests/arch/gowin/mux.ys | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index d612e4eaa..1cb3d53e6 100644
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT4
@@ -27,7 +27,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 5 t:LUT4
@@ -39,7 +39,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 10 t:LUT4
-- 
cgit v1.2.3


From 903f9973913371452005eb173ac50fec1d5d1447 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 15:18:01 +0100
Subject: add tristate buffer and test

---
 techlibs/gowin/cells_sim.v    |  6 ++++++
 techlibs/gowin/synth_gowin.cc |  4 ++--
 tests/arch/gowin/tribuf.ys    | 13 +++++++++++++
 3 files changed, 21 insertions(+), 2 deletions(-)
 create mode 100644 tests/arch/gowin/tribuf.ys

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 0fe2c8c52..cc1ac48e6 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -302,6 +302,12 @@ module OBUF(output O, input I);
 	assign O = I;
 endmodule
 
+module TBUF (O, I, OEN);
+  input I, OEN;
+  output O;
+  assign O = OEN ? I : 1'bz;
+endmodule
+
 module GSR (input GSRI);
 	wire GSRO = GSRI;
 endmodule
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index e9b2ccded..d541edd84 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -174,7 +174,7 @@ struct SynthGowinPass : public ScriptPass
 			run("synth -run coarse");
 		}
 		
-                if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/gowin/bram.txt");
 			run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
@@ -230,7 +230,7 @@ struct SynthGowinPass : public ScriptPass
 			run("techmap -map +/gowin/cells_map.v");
 			run("setundef -undriven -params -zero");
 			run("hilomap -singleton -hicell VCC V -locell GND G");
-			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
+			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)");
 			run("dffinit  -ff DFF Q INIT");
 			run("clean");
 
diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys
new file mode 100644
index 000000000..5855b9d97
--- /dev/null
+++ b/tests/arch/gowin/tribuf.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+#Internal cell type used. Need support it.
+select -assert-count 1 t:TBUF
+select -assert-count 2 t:IBUF
+select -assert-none t:TBUF t:IBUF %% t:* %D
-- 
cgit v1.2.3


From 0f6269b04c4a5f44b62021759507bcbe61a7c8d7 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 28 Oct 2019 15:33:05 +0100
Subject: add IOBUF

---
 techlibs/gowin/cells_sim.v    | 8 ++++++++
 techlibs/gowin/synth_gowin.cc | 3 ++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index cc1ac48e6..a67855dab 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -308,6 +308,14 @@ module TBUF (O, I, OEN);
   assign O = OEN ? I : 1'bz;
 endmodule
 
+module IOBUF (O, IO, I, OEN);
+  input I,OEN;
+  output O;
+  inout IO;
+  assign IO = OEN ? I : 1'bz;
+  assign I = IO;
+endmodule
+
 module GSR (input GSRI);
 	wire GSRO = GSRI;
 endmodule
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index d541edd84..a70ff93bb 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -230,7 +230,8 @@ struct SynthGowinPass : public ScriptPass
 			run("techmap -map +/gowin/cells_map.v");
 			run("setundef -undriven -params -zero");
 			run("hilomap -singleton -hicell VCC V -locell GND G");
-			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)");
+			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
+				"-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
 			run("dffinit  -ff DFF Q INIT");
 			run("clean");
 
-- 
cgit v1.2.3


From df8390f5df9868b583ce88a4d2ce41511fab2f7b Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 30 Oct 2019 14:58:25 +0100
Subject: don't cound exact luts in big muxes; futile and fragile

---
 tests/arch/gowin/mux.ys | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index 1cb3d53e6..f7e478c87 100644
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -30,7 +30,6 @@ proc
 equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 5 t:LUT4
 select -assert-count 11 t:IBUF
 select -assert-count 1 t:OBUF
 
@@ -42,8 +41,6 @@ proc
 equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 10 t:LUT4
-select -assert-count 1 t:LUT3
 select -assert-count 20 t:IBUF
 select -assert-count 1 t:OBUF
 
-- 
cgit v1.2.3


From 0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Wed, 6 Nov 2019 19:48:18 +0100
Subject: fix wide luts

---
 techlibs/gowin/cells_map.v | 24 ++++++++++++------------
 tests/arch/gowin/mux.ys    | 17 ++++++++++-------
 2 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 62cb080d9..93a49679c 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -104,27 +104,27 @@ module \$lut (A, Y);
     end else
     if (WIDTH == 5) begin
       wire f0, f1;
-      \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0));
-      \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1));
-      MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+      \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
+      \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
+      MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
     end else
     if (WIDTH == 6) begin
       wire f0, f1;
-      \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0));
-      \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1));
-      MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+      \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
+      \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
+      MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
     end else
     if (WIDTH == 7) begin
       wire f0, f1;
-      \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0));
-      \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1));
-      MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+      \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
+      \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
+      MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
     end else
     if (WIDTH == 8) begin
       wire f0, f1;
-      \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0));
-      \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1));
-      MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+      \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
+      \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
+      MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index f7e478c87..4990be421 100644
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -15,33 +15,36 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 2 t:LUT4
+select -assert-count 4 t:LUT4
+select -assert-count 2 t:MUX2_LUT5
+select -assert-count 1 t:MUX2_LUT6
 select -assert-count 6 t:IBUF
 select -assert-count 1 t:OBUF
 
-select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
 
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 11 t:IBUF
 select -assert-count 1 t:OBUF
 
-select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
 
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 20 t:IBUF
 select -assert-count 1 t:OBUF
+show
 
-select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
-- 
cgit v1.2.3


From ab8c521030a2c91a1e388d6f3c627a7f7dd525b2 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 11 Nov 2019 17:51:26 +0100
Subject: fix fsm test with proper clock enable polarity

---
 techlibs/gowin/cells_map.v |  8 ++++----
 tests/arch/gowin/fsm.ys    | 11 +++++++++++
 2 files changed, 15 insertions(+), 4 deletions(-)
 create mode 100644 tests/arch/gowin/fsm.ys

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 93a49679c..881c2e9bb 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -23,11 +23,11 @@ module  \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D),
 
 // DFFRE     D Flip-Flop with Clock Enable and Synchronous Reset
 module  \$__DFFSE_PN0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule
-module  \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule
+module  \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule
 
 // DFFNRE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
 module  \$__DFFNSE_PN0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule
-module  \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule
+module  \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule
 
 // DFFS      D Flip-Flop with Synchronous Set
 module  \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
@@ -39,11 +39,11 @@ module  \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D),
 
 // DFFSE     D Flip-Flop with Clock Enable and Synchronous Set
 module  \$__DFFSE_PN1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule
-module  \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule
+module  \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule
 
 // DFFNSE    D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
 module  \$__DFFSE_NN1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule
-module  \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule
+module  \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule
 
 // DFFP      D Flip-Flop with Asynchronous Preset
 module  \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
diff --git a/tests/arch/gowin/fsm.ys b/tests/arch/gowin/fsm.ys
new file mode 100644
index 000000000..ce4504522
--- /dev/null
+++ b/tests/arch/gowin/fsm.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+#design -load postopt
+#shell
-- 
cgit v1.2.3


From dd8c7e1ddda152e9c06d4b950564eb4aa1051c98 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 18 Nov 2019 14:25:46 +0100
Subject: add help for nowidelut and abc9 options

---
 techlibs/gowin/synth_gowin.cc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index a70ff93bb..bb6d44e00 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -64,6 +64,12 @@ struct SynthGowinPass : public ScriptPass
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
+		log("    -nowidelut\n");
+		log("        do not use muxes to implement LUTs larger than LUT4s\n");
+		log("\n");
+		log("    -abc9\n");
+		log("        use new ABC9 flow (EXPERIMENTAL)\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -173,7 +179,7 @@ struct SynthGowinPass : public ScriptPass
 		{
 			run("synth -run coarse");
 		}
-		
+
 		if (!nobram && check_label("bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/gowin/bram.txt");
-- 
cgit v1.2.3


From 8ab412eb16b1d4f98117247bf85e0c37627ee459 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Tue, 19 Nov 2019 15:53:44 +0100
Subject: Remove dff init altogether

The hardware does not actually support it.
In reality it is always initialised to its reset value.
---
 techlibs/gowin/cells_map.v    | 5 +++--
 techlibs/gowin/synth_gowin.cc | 1 -
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 881c2e9bb..9845e56a7 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -1,9 +1,10 @@
-//TODO all DFF* have INIT
+//All DFF* have INIT, but the hardware is always initialised to the reset
+//value regardless. The parameter is ignored.
 
 // DFFN      D Flip-Flop with Negative-Edge Clock
 module  \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
 // DFF       D Flip-Flop
-module  \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF  #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
 
 // DFFE      D Flip-Flop with Clock Enable
 module  \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index bb6d44e00..3c1426414 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -238,7 +238,6 @@ struct SynthGowinPass : public ScriptPass
 			run("hilomap -singleton -hicell VCC V -locell GND G");
 			run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
 				"-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
-			run("dffinit  -ff DFF Q INIT");
 			run("clean");
 
 		}
-- 
cgit v1.2.3