From 7cb56f34b06de666935fbda315ce7c7bd45048b3 Mon Sep 17 00:00:00 2001 From: Lukasz Dalek Date: Mon, 18 May 2020 21:01:16 +0200 Subject: Fix integer signing grammar This commit fixes signed/unsigned grammar in parameters as defined in SV LRM A2.2.1. Example of correct parameters: parameter integer signed i = 0; parameter integer unsigned i = 0; Example of incorrect parameters: parameter signed integer i = 0; parameter unsigned integer i = 0; Signed-off-by: Lukasz Dalek Signed-off-by: Kamil Rakoczy --- frontends/verilog/verilog_parser.y | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 15c231f3b..18745e38e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1329,6 +1329,8 @@ ignspec_id: param_signed: TOK_SIGNED { astbuf1->is_signed = true; + } | TOK_UNSIGNED { + astbuf1->is_signed = false; } | /* empty */; param_integer: @@ -1339,14 +1341,14 @@ param_integer: astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true)); astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true)); astbuf1->is_signed = true; - } | /* empty */; + } param_real: TOK_REAL { if (astbuf1->children.size() != 1) frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real."); astbuf1->children.push_back(new AstNode(AST_REALVALUE)); - } | /* empty */; + } param_range: range { @@ -1357,8 +1359,12 @@ param_range: } }; +param_integer_type: param_integer param_signed +param_range_type: type_vec param_signed param_range +param_implicit_type: param_signed param_range + param_type: - param_signed param_integer param_real param_range | + param_integer_type | param_real | param_range_type | param_implicit_type | hierarchical_type_id { astbuf1->is_custom_type = true; astbuf1->children.push_back(new AstNode(AST_WIRETYPE)); -- cgit v1.2.3 From 6f9be939bd7653b0bdcae93a1033a086a4561b68 Mon Sep 17 00:00:00 2001 From: Lukasz Dalek Date: Mon, 1 Jun 2020 15:25:24 +0200 Subject: Parse macro call attached semicolon as empty expression Signed-off-by: Lukasz Dalek --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 18745e38e..35e34a124 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -745,7 +745,7 @@ module_body: module_body_stmt: task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | enum_decl | struct_decl | - always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block; + always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';'; checker_decl: TOK_CHECKER TOK_ID ';' { -- cgit v1.2.3 From 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Fri, 26 Jun 2020 15:35:35 +0200 Subject: Add signed/unsigned tests Signed-off-by: Kamil Rakoczy --- tests/various/signed.ys | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 tests/various/signed.ys diff --git a/tests/various/signed.ys b/tests/various/signed.ys new file mode 100644 index 000000000..2319a5da1 --- /dev/null +++ b/tests/various/signed.ys @@ -0,0 +1,28 @@ +# SV LRM A2.2.1 + +read_verilog -sv <