From 6d27d4372730cb94306a4f314482459f9d527d7c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 Jan 2020 10:37:16 -0800 Subject: Add and use SigSpec::reverse() --- frontends/aiger/aigerparse.cc | 6 +++--- kernel/rtlil.h | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index f92a11c6d..a42569301 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -410,7 +410,7 @@ void AigerReader::parse_xaiger() RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)); log_assert(output_sig); uint32_t nodeID; - std::vector input_bits; + RTLIL::SigSpec input_sig; for (unsigned j = 0; j < cutLeavesM; ++j) { nodeID = parse_xaiger_literal(f); log_debug2("\t%u\n", nodeID); @@ -420,10 +420,10 @@ void AigerReader::parse_xaiger() } RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID)); log_assert(wire); - input_bits.push_back(wire); + input_sig.append(wire); } // Reverse input order as fastest input is returned first - RTLIL::SigSpec input_sig(std::vector(input_bits.rbegin(), input_bits.rend())); + input_sig.reverse(); // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size()) ce.clear(); ce.compute_deps(output_sig, input_sig.to_sigbit_pool()); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6251d265d..58c5d9674 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -851,6 +851,8 @@ public: RTLIL::SigSpec repeat(int num) const; + void reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); } + bool operator <(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const; inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } -- cgit v1.2.3