From 65c022c2572036a66bd06bafd3e3efa088aafb79 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 20:41:14 -0700
Subject: Remove DFF and RAMD box info for now

---
 techlibs/xilinx/abc_xc7.box | 34 ----------------------------------
 techlibs/xilinx/cells_sim.v |  2 --
 2 files changed, 36 deletions(-)

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 8a48bad4e..c9d80a333 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -26,37 +26,3 @@ CARRY4 3 1 10 8
 433 469 -   -   494 465 445 -   -   157
 512 548 292 -   592 540 520 356 -   228
 508 528 378 380 580 526 507 398 385 114
-
-# SLICEM/A6LUT
-# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
-# Outputs: DPO SPO
-RAM64X1D 4 0 15 2
--   -   -   -   -   -   - 124 124 124 124 124 124 - -
-124 124 124 124 124 124 - -   -   -   -   -   124 - -
-
-# SLICEM/A6LUT + F7[AB]MUX
-# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
-# Outputs: DPO SPO
-RAM128X1D 5 0 17 2
--   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
-347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
-
-# Inputs: C CE D R
-# Outputs: Q
-FDRE 6 0 4 1
-- - - -
-
-# Inputs: C CE D S
-# Outputs: Q
-FDSE 7 0 4 1
-- - - -
-
-# Inputs: C CE CLR D
-# Outputs: Q
-FDCE 8 0 4 1
-- - - -
-
-# Inputs: C CE D PRE
-# Outputs: Q
-FDPE 9 0 4 1
-- - - -
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index bf7a0ed44..84939818e 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -281,7 +281,6 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-//(* abc_box_id = 4 /*, lib_whitebox*/ *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -299,7 +298,6 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-//(* abc_box_id = 5 /*, lib_whitebox*/ *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,
-- 
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