From 9286acb6870876f27771c039704ded7d9ffef3a9 Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Sun, 13 May 2018 16:53:35 -0400 Subject: Add option -expose to setundef pass Option -expose converts undriven wires to inputs. Example usage: setundef -undriven -expose [selection] --- passes/cmds/setundef.cc | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index c11ddbdc1..172b1c3f8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -81,6 +81,9 @@ struct SetundefPass : public Pass { log(" -undriven\n"); log(" also set undriven nets to constant values\n"); log("\n"); + log(" -expose\n"); + log(" also expose undriven nets as inputs\n"); + log("\n"); log(" -zero\n"); log(" replace with bits cleared (0)\n"); log("\n"); @@ -105,6 +108,7 @@ struct SetundefPass : public Pass { { bool got_value = false; bool undriven_mode = false; + bool expose_mode = false; bool init_mode = false; SetundefWorker worker; @@ -117,6 +121,11 @@ struct SetundefPass : public Pass { undriven_mode = true; continue; } + if (args[argidx] == "-expose") { + got_value = true; + expose_mode = true; + continue; + } if (args[argidx] == "-zero") { got_value = true; worker.next_bit_mode = 0; @@ -157,6 +166,8 @@ struct SetundefPass : public Pass { } extra_args(args, argidx, design); + if (expose_mode && !undriven_mode) + log_cmd_error("Option -expose must be used with option -undriven.\n"); if (!got_value) log_cmd_error("One of the options -zero, -one, -anyseq, or -random must be specified.\n"); @@ -184,12 +195,21 @@ struct SetundefPass : public Pass { undriven_signals.del(sigmap(conn.second)); RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks()) { - RTLIL::SigSpec bits; - for (int i = 0; i < c.width; i++) - bits.append(worker.next_bit()); - module->connect(RTLIL::SigSig(c, bits)); - } + if (expose_mode) { + for (auto &c : sig.chunks()) { + c.wire->port_input = true; + log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(c.wire->name)); + } + module->fixup_ports(); + } + else { + for (auto &c : sig.chunks()) { + RTLIL::SigSpec bits; + for (int i = 0; i < c.width; i++) + bits.append(worker.next_bit()); + module->connect(RTLIL::SigSig(c, bits)); + } + } } if (init_mode) -- cgit v1.2.3 From b4a303a1b7a9986881efa1040bf54c5f583d87a0 Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Sun, 13 May 2018 20:13:54 -0400 Subject: Corrections to option -expose in setundef pass --- passes/cmds/setundef.cc | 157 +++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 141 insertions(+), 16 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 172b1c3f8..0825cf83e 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -26,6 +26,70 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global) +{ + RTLIL::Wire *wire = NULL; + name = RTLIL::escape_id(name); + + if (module->count_id(name) != 0) + { + if (module->wires_.count(name) > 0) + wire = module->wires_.at(name); + + if (wire != NULL && wire->width != width) + wire = NULL; + + if (wire != NULL && wire->port_input != flag_input) + wire = NULL; + + if (wire != NULL && wire->port_output != flag_output) + wire = NULL; + + if (wire == NULL) { + return wire; + log_cmd_error("Found incompatible object %s with same name in module %s!\n", name.c_str(), module->name.c_str()); + } + + log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str()); + } + else + { + wire = module->addWire(name, width); + wire->port_input = flag_input; + wire->port_output = flag_output; + + if (flag_input || flag_output) { + wire->port_id = module->wires_.size(); + module->fixup_ports(); + } + + log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); + } + + if (!flag_global) + return wire; + + for (auto &it : module->cells_) + { + if (design->modules_.count(it.second->type) == 0) + continue; + + RTLIL::Module *mod = design->modules_.at(it.second->type); + if (!design->selected_whole_module(mod->name)) + continue; + if (mod->get_bool_attribute("\\blackbox")) + continue; + if (it.second->hasPort(name)) + continue; + + it.second->setPort(name, wire); + log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); + } + + return wire; +} + + struct SetundefWorker { int next_bit_mode; @@ -178,31 +242,92 @@ struct SetundefPass : public Pass { if (!module->processes.empty()) log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n"); - SigMap sigmap(module); - SigPool undriven_signals; + if (expose_mode) { + SigMap sigmap(module); + dict wire_drivers; + pool used_wires; + SigPool undriven_signals; + + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) { + SigSpec sig = sigmap(conn.second); + if (cell->input(conn.first)) + for (auto bit : sig) + if (bit.wire) { + used_wires.insert(bit); + } + if (cell->output(conn.first)) + for (int i = 0; i < GetSize(sig); i++) { + if (sig[i].wire) + wire_drivers[sig[i]] = true; + } + } + + for (auto wire : module->wires()) { + if (wire->port_input) { + SigSpec sig = sigmap(wire); + for (int i = 0; i < GetSize(sig); i++) + wire_drivers[sig[i]] = true; + } + if (wire->port_output) + for (auto bit : sigmap(wire)) + if (bit.wire) used_wires.insert(bit); + } - for (auto &it : module->wires_) - undriven_signals.add(sigmap(it.second)); + pool undriven_wires; + for (auto bit : used_wires) { + if (!wire_drivers.count(bit)) { + undriven_wires.insert(bit.wire); + } + } - for (auto &it : module->wires_) - if (it.second->port_input) - undriven_signals.del(sigmap(it.second)); + for (auto &it : undriven_wires) + undriven_signals.add(sigmap(it)); - CellTypes ct(design); - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) - undriven_signals.del(sigmap(conn.second)); + for (auto &it : undriven_wires) + if (it->port_input) + undriven_signals.del(sigmap(it)); - RTLIL::SigSpec sig = undriven_signals.export_all(); - if (expose_mode) { + CellTypes ct(design); + for (auto &it : module->cells_) + for (auto &conn : it.second->connections()) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); + + RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { - c.wire->port_input = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(c.wire->name)); + RTLIL::Wire * wire; + if (c.wire->width == c.width) { + wire = c.wire; + wire->port_input = true; + } + else { + string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; + wire = add_wire(design, module, name, c.width, true, false, false); + module->connect(RTLIL::SigSig(c.wire, wire)); + } + log("Exposing undriven wire %s as input.\n", wire->name.c_str()); } module->fixup_ports(); } else { + SigMap sigmap(module); + SigPool undriven_signals; + + for (auto &it : module->wires_) + undriven_signals.add(sigmap(it.second)); + + for (auto &it : module->wires_) + if (it.second->port_input) + undriven_signals.del(sigmap(it.second)); + + CellTypes ct(design); + for (auto &it : module->cells_) + for (auto &conn : it.second->connections()) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); + + RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) -- cgit v1.2.3 From 8b9a8c7f9115e691dc832b3be3d82b55be507e99 Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Mon, 14 May 2018 18:58:49 -0400 Subject: Minor correction Minor typo error correction in -expose with setundef --- passes/cmds/setundef.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 0825cf83e..9b0c30cae 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -89,7 +89,6 @@ static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std: return wire; } - struct SetundefWorker { int next_bit_mode; @@ -304,7 +303,7 @@ struct SetundefPass : public Pass { else { string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; wire = add_wire(design, module, name, c.width, true, false, false); - module->connect(RTLIL::SigSig(c.wire, wire)); + module->connect(RTLIL::SigSig(c, wire)); } log("Exposing undriven wire %s as input.\n", wire->name.c_str()); } -- cgit v1.2.3 From 6e63df6dd08fe424f46039d26f9f238ac1cb4494 Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Tue, 15 May 2018 13:06:23 -0400 Subject: Correction to -expose with setundef --- passes/cmds/setundef.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 9b0c30cae..c67953976 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -308,6 +308,7 @@ struct SetundefPass : public Pass { log("Exposing undriven wire %s as input.\n", wire->name.c_str()); } module->fixup_ports(); + continue; } else { SigMap sigmap(module); -- cgit v1.2.3 From 83b41260f6c8dd3ba617cc03b06435521038e7db Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Sat, 18 Aug 2018 09:08:07 +0530 Subject: Revision to expose option in setundef pass Corrects indentation Simplifications and corrections --- passes/cmds/setundef.cc | 277 +++++++++++++++++++++--------------------------- 1 file changed, 123 insertions(+), 154 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index eac1f6236..62d940ce6 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -33,67 +33,32 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global) +static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output) { - RTLIL::Wire *wire = NULL; - name = RTLIL::escape_id(name); - - if (module->count_id(name) != 0) - { - if (module->wires_.count(name) > 0) - wire = module->wires_.at(name); - - if (wire != NULL && wire->width != width) - wire = NULL; - - if (wire != NULL && wire->port_input != flag_input) - wire = NULL; - - if (wire != NULL && wire->port_output != flag_output) - wire = NULL; - - if (wire == NULL) { - return wire; - log_cmd_error("Found incompatible object %s with same name in module %s!\n", name.c_str(), module->name.c_str()); - } - - log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str()); - } - else - { - wire = module->addWire(name, width); - wire->port_input = flag_input; - wire->port_output = flag_output; - - if (flag_input || flag_output) { - wire->port_id = module->wires_.size(); - module->fixup_ports(); - } - - log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); - } - - if (!flag_global) - return wire; - - for (auto &it : module->cells_) - { - if (design->modules_.count(it.second->type) == 0) - continue; - - RTLIL::Module *mod = design->modules_.at(it.second->type); - if (!design->selected_whole_module(mod->name)) - continue; - if (mod->get_bool_attribute("\\blackbox")) - continue; - if (it.second->hasPort(name)) - continue; - - it.second->setPort(name, wire); - log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); - } - - return wire; + RTLIL::Wire *wire = NULL; + name = RTLIL::escape_id(name); + + if (module->count_id(name) != 0) + { + log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str()); + name += "$"; + return add_wire(module, name, width, flag_input, flag_output); + } + else + { + wire = module->addWire(name, width); + wire->port_input = flag_input; + wire->port_output = flag_output; + + if (flag_input || flag_output) { + wire->port_id = module->wires_.size(); + module->fixup_ports(); + } + + log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); + } + + return wire; } struct SetundefWorker @@ -262,100 +227,104 @@ struct SetundefPass : public Pass { if (!module->processes.empty()) log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n"); - if (expose_mode) { - SigMap sigmap(module); - dict wire_drivers; - pool used_wires; - SigPool undriven_signals; - - for (auto cell : module->cells()) - for (auto &conn : cell->connections()) { - SigSpec sig = sigmap(conn.second); - if (cell->input(conn.first)) - for (auto bit : sig) - if (bit.wire) { - used_wires.insert(bit); - } - if (cell->output(conn.first)) - for (int i = 0; i < GetSize(sig); i++) { - if (sig[i].wire) - wire_drivers[sig[i]] = true; - } - } - - for (auto wire : module->wires()) { - if (wire->port_input) { - SigSpec sig = sigmap(wire); - for (int i = 0; i < GetSize(sig); i++) - wire_drivers[sig[i]] = true; - } - if (wire->port_output) - for (auto bit : sigmap(wire)) - if (bit.wire) used_wires.insert(bit); - } - - pool undriven_wires; - for (auto bit : used_wires) { - if (!wire_drivers.count(bit)) { - undriven_wires.insert(bit.wire); - } - } - - for (auto &it : undriven_wires) - undriven_signals.add(sigmap(it)); - - for (auto &it : undriven_wires) - if (it->port_input) - undriven_signals.del(sigmap(it)); - - CellTypes ct(design); - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) - undriven_signals.del(sigmap(conn.second)); - - RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks()) { - RTLIL::Wire * wire; - if (c.wire->width == c.width) { - wire = c.wire; - wire->port_input = true; - } - else { - string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; - wire = add_wire(design, module, name, c.width, true, false, false); - module->connect(RTLIL::SigSig(c, wire)); - } - log("Exposing undriven wire %s as input.\n", wire->name.c_str()); - } - module->fixup_ports(); - continue; - } - else { - SigMap sigmap(module); - SigPool undriven_signals; - - for (auto &it : module->wires_) - undriven_signals.add(sigmap(it.second)); - - for (auto &it : module->wires_) - if (it.second->port_input) - undriven_signals.del(sigmap(it.second)); - - CellTypes ct(design); - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) - undriven_signals.del(sigmap(conn.second)); - - RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks()) { - RTLIL::SigSpec bits; - for (int i = 0; i < c.width; i++) - bits.append(worker.next_bit()); - module->connect(RTLIL::SigSig(c, bits)); - } - } + if (expose_mode) + { + SigMap sigmap(module); + dict wire_drivers; + pool used_wires; + SigPool undriven_signals; + + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) { + SigSpec sig = sigmap(conn.second); + if (cell->input(conn.first)) + for (auto bit : sig) + if (bit.wire) + used_wires.insert(bit); + if (cell->output(conn.first)) + for (int i = 0; i < GetSize(sig); i++) + if (sig[i].wire) + wire_drivers[sig[i]] = true; + } + + for (auto wire : module->wires()) { + if (wire->port_input) { + SigSpec sig = sigmap(wire); + for (int i = 0; i < GetSize(sig); i++) + wire_drivers[sig[i]] = true; + } + if (wire->port_output) { + SigSpec sig = sigmap(wire); + for (auto bit : sig) + if (bit.wire) + used_wires.insert(bit); + } + } + + pool undriven_wires; + for (auto bit : used_wires) + if (!wire_drivers.count(bit)) + undriven_wires.insert(bit.wire); + + for (auto &it : undriven_wires) + undriven_signals.add(sigmap(it)); + + for (auto &it : undriven_wires) + if (it->port_input) + undriven_signals.del(sigmap(it)); + + CellTypes ct(design); + for (auto &it : module->cells_) + for (auto &conn : it.second->connections()) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); + + RTLIL::SigSpec sig = undriven_signals.export_all(); + for (auto &c : sig.chunks()) { + RTLIL::Wire * wire; + if (c.wire->width == c.width) { + wire = c.wire; + wire->port_input = true; + } else { + string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; + wire = add_wire(module, name, c.width, true, false); + module->connect(RTLIL::SigSig(c, wire)); + } + log("Exposing undriven wire %s as input.\n", wire->name.c_str()); + } + module->fixup_ports(); + } + else + { + SigMap sigmap(module); + SigPool undriven_signals; + + for (auto &it : module->wires_) + undriven_signals.add(sigmap(it.second)); + + for (auto &it : module->wires_) + if (it.second->port_input) + undriven_signals.del(sigmap(it.second)); + + CellTypes ct(design); + for (auto &it : module->cells_) + for (auto &conn : it.second->connections()) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); + + RTLIL::SigSpec sig = undriven_signals.export_all(); + for (auto &c : sig.chunks()) { + RTLIL::SigSpec bits; + if (worker.next_bit_mode == MODE_ANYSEQ) + bits = module->Anyseq(NEW_ID, c.width); + else if (worker.next_bit_mode == MODE_ANYCONST) + bits = module->Anyconst(NEW_ID, c.width); + else + for (int i = 0; i < c.width; i++) + bits.append(worker.next_bit()); + module->connect(RTLIL::SigSig(c, bits)); + } + } } if (init_mode) -- cgit v1.2.3