From 40563129872f5a2287f54cb0dbd79534b493a5d6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 27 Jul 2016 15:41:22 +0200 Subject: Added $anyconst and $aconst --- frontends/ast/genrtlil.cc | 45 ++++++++++++++++++++++++++++++++++++++ frontends/ast/simplify.cc | 4 ++++ frontends/verilog/verilog_parser.y | 2 +- kernel/celltypes.h | 2 ++ kernel/rtlil.cc | 6 +++++ manual/CHAPTER_CellLib.tex | 2 +- techlibs/common/simlib.v | 24 ++++++++++++++++++++ 7 files changed, 83 insertions(+), 2 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 2fb95ff5a..04cdb9416 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -750,6 +750,19 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun width_hint = max(width_hint, this_width); break; + case AST_FCALL: + if (str == "\\$anyconst" || str == "\\$aconst") { + if (GetSize(children) == 1) { + while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } + if (children[0]->type != AST_CONSTANT) + log_error("System function %s called with non-const argument at %s:%d!\n", + RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + width_hint = max(width_hint, int(children[0]->asInt(true))); + } + break; + } + /* fall through */ + // everything should have been handled above -> print error if not. default: for (auto f : log_files) @@ -1427,6 +1440,38 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) delete always; } break; + case AST_FCALL: { + if (str == "\\$anyconst" || str == "\\$aconst") + { + string myid = stringf("%s$%d", RTLIL::unescape_id(str).c_str(), autoidx++); + int width = width_hint; + + if (GetSize(children) > 1) + log_error("System function %s got %d arguments, expected 1 or 0 at %s:%d.\n", + RTLIL::unescape_id(str).c_str(), GetSize(children), filename.c_str(), linenum); + + if (GetSize(children) == 1) { + if (children[0]->type != AST_CONSTANT) + log_error("System function %s called with non-const argument at %s:%d!\n", + RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + width = children[0]->asInt(true); + } + + if (width <= 0) + log_error("Failed to detect width of %s at %s:%d!\n", + RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + + Cell *cell = current_module->addCell(myid, str.substr(1)); + cell->parameters["\\WIDTH"] = width; + + Wire *wire = current_module->addWire(myid + "_wire", width); + cell->setPort("\\Y", wire); + + is_signed = sign_hint; + return SigSpec(wire); + } + } /* fall through */ + // everything should have been handled above -> print error if not. default: for (auto f : log_files) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 9f88cddc2..79dc3b7c8 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1655,6 +1655,10 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } + // $anyconst and $aconst are mapped in AstNode::genRTLIL() + if (str == "\\$anyconst" || str == "\\$aconst") + return false; + if (str == "\\$clog2") { if (children.size() != 1) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4cb65a088..c2327011f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1219,7 +1219,7 @@ rvalue: $$ = new AstNode(AST_IDENTIFIER, $2); $$->str = *$1; delete $1; - if ($2 == nullptr && $$->str == "\\$initstate") + if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$aconst")) $$->type = AST_FCALL; } | hierarchical_id non_opt_multirange { diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 1eea0530c..9eb1523e9 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -118,6 +118,8 @@ struct CellTypes setup_type("$assume", {A, EN}, pool(), true); setup_type("$predict", {A, EN}, pool(), true); setup_type("$initstate", pool(), {Y}, true); + setup_type("$anyconst", pool(), {Y}, true); + setup_type("$aconst", pool(), {Y}, true); setup_type("$equiv", {A, B}, {Y}, true); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2e5157e85..ad90965fb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1030,6 +1030,12 @@ namespace { return; } + if (cell->type.in("$aconst", "$anyconst")) { + port("\\Y", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$equiv") { port("\\A", 1); port("\\B", 1); diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 0f1136346..bff01d06c 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, {\tt \$equiv}, and {\tt \$initstate} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$aconst}, and {\tt \$anyconst} cells. \end{fixme} \begin{fixme} diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 8ab124034..ac4269c90 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1330,6 +1330,30 @@ endmodule // -------------------------------------------------------- +module \$aconst (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + +module \$anyconst (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; -- cgit v1.2.3