From 2e3647f5672e375b3f00a8a4c6db87d376393724 Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Tue, 14 Apr 2020 00:35:47 +0000
Subject: Use `dict` instead of `std::map`.

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
---
 passes/cmds/rename.cc | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index afc23b0a1..7d6d84d42 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -213,16 +213,16 @@ struct RenamePass : public Pass {
 			for (auto module : design->selected_modules())
 			{
 				int counter = 0;
-				std::map<RTLIL::Wire *, IdString> new_wire_names;
-				std::map<RTLIL::Cell *, IdString> new_cell_names;
+				dict<RTLIL::Wire *, IdString> new_wire_names;
+				dict<RTLIL::Cell *, IdString> new_cell_names;
 
 				for (auto wire : module->selected_wires())
 					if (wire->name[0] == '$')
-						new_wire_names[wire] = derive_name_from_src(wire->get_src_attribute(), counter++);
+						new_wire_names.emplace(wire, derive_name_from_src(wire->get_src_attribute(), counter++));
 
 				for (auto cell : module->selected_cells())
 					if (cell->name[0] == '$')
-						new_cell_names[cell] = derive_name_from_src(cell->get_src_attribute(), counter++);
+						new_cell_names.emplace(cell, derive_name_from_src(cell->get_src_attribute(), counter++));
 
 				for (auto &it : new_wire_names)
 					module->rename(it.first, it.second);
@@ -237,7 +237,7 @@ struct RenamePass : public Pass {
 			extra_args(args, argidx, design);
 
 			for (auto module : design->selected_modules()) {
-				std::map<RTLIL::Cell *, IdString> new_cell_names;
+				dict<RTLIL::Cell *, IdString> new_cell_names;
 				for (auto cell : module->selected_cells())
 					if (cell->name[0] == '$')
 						new_cell_names[cell] = derive_name_from_cell_output_wire(cell);
@@ -253,8 +253,8 @@ struct RenamePass : public Pass {
 			for (auto module : design->selected_modules())
 			{
 				int counter = 0;
-				std::map<RTLIL::Wire *, IdString> new_wire_names;
-				std::map<RTLIL::Cell *, IdString> new_cell_names;
+				dict<RTLIL::Wire *, IdString> new_wire_names;
+				dict<RTLIL::Cell *, IdString> new_cell_names;
 
 				for (auto wire : module->selected_wires())
 					if (wire->name[0] == '$') {
@@ -286,8 +286,8 @@ struct RenamePass : public Pass {
 
 			for (auto module : design->selected_modules())
 			{
-				std::map<RTLIL::Wire *, IdString> new_wire_names;
-				std::map<RTLIL::Cell *, IdString> new_cell_names;
+				dict<RTLIL::Wire *, IdString> new_wire_names;
+				dict<RTLIL::Cell *, IdString> new_cell_names;
 
 				for (auto wire : module->selected_wires())
 					if (wire->name[0] == '\\' && wire->port_id == 0)
-- 
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