From 1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57 Mon Sep 17 00:00:00 2001
From: Robert Ou <rqou@robertou.com>
Date: Tue, 1 Aug 2017 11:58:01 -0700
Subject: coolrunner2: Add FFs with clock enable to cells_sim.v

---
 techlibs/coolrunner2/cells_sim.v | 60 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index e08ee5f9b..d8dca1922 100644
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -244,3 +244,63 @@ module FTDCP (C, PRE, CLR, T, Q);
 
     assign Q = Q_;
 endmodule
+
+module FDCPE (C, PRE, CLR, D, Q, CE);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, D, CE;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @(posedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (PRE == 1)
+            Q <= 1;
+        else if (CE == 1)
+            Q <= D;
+    end
+endmodule
+
+module FDCPE_N (C, PRE, CLR, D, Q, CE);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, D, CE;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @(negedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (PRE == 1)
+            Q <= 1;
+        else if (CE == 1)
+            Q <= D;
+    end
+endmodule
+
+module FDDCPE (C, PRE, CLR, D, Q, CE);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, D, CE;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (PRE == 1)
+            Q <= 1;
+        else if (CE == 1)
+            Q <= D;
+    end
+endmodule
-- 
cgit v1.2.3


From 78fd24f40f1e2be64e8ea8116a8a2277cb3a9baf Mon Sep 17 00:00:00 2001
From: Robert Ou <rqou@robertou.com>
Date: Mon, 7 Aug 2017 04:01:18 -0700
Subject: coolrunner2: Add INVERT parameter to some BUFGs

---
 techlibs/coolrunner2/cells_sim.v | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index d8dca1922..562fb1efd 100644
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -143,17 +143,21 @@ module BUFG(I, O);
 endmodule
 
 module BUFGSR(I, O);
+    parameter INVERT = 0;
+
     input I;
     output O;
 
-    assign O = I;
+    assign O = INVERT ? ~I : I;
 endmodule
 
 module BUFGTS(I, O);
+    parameter INVERT = 0;
+
     input I;
     output O;
 
-    assign O = I;
+    assign O = INVERT ? ~I : I;
 endmodule
 
 module FDDCP (C, PRE, CLR, D, Q);
-- 
cgit v1.2.3