From 21659847a7a31f80140e03a5b6351da54c062836 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 8 Jul 2016 14:41:36 +0200 Subject: Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations --- techlibs/ice40/ice40_ffinit.cc | 30 ++++++++++++++++++------------ techlibs/ice40/ice40_ffssr.cc | 7 ++++++- 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index 8a2c30d6a..c914b20e8 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -101,17 +101,23 @@ struct Ice40FfinitPass : public Pass { if (!sb_dff_types.count(cell->type)) continue; - SigBit sig_d = sigmap(cell->getPort("\\D")); - SigBit sig_q = sigmap(cell->getPort("\\Q")); + SigSpec sig_d = cell->getPort("\\D"); + SigSpec sig_q = cell->getPort("\\Q"); - if (!initbits.count(sig_q)) + if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1) continue; - State val = initbits.at(sig_q); - handled_initbits.insert(sig_q); + SigBit bit_d = sigmap(sig_d[0]); + SigBit bit_q = sigmap(sig_q[0]); + + if (!initbits.count(bit_q)) + continue; + + State val = initbits.at(bit_q); + handled_initbits.insert(bit_q); log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type), - log_signal(sig_q), val != State::S0 ? '1' : '0'); + log_signal(bit_q), val != State::S0 ? '1' : '0'); if (val == State::S0) continue; @@ -131,14 +137,14 @@ struct Ice40FfinitPass : public Pass { cell->unsetPort("\\R"); } - Wire *new_sig_d = module->addWire(NEW_ID); - Wire *new_sig_q = module->addWire(NEW_ID); + Wire *new_bit_d = module->addWire(NEW_ID); + Wire *new_bit_q = module->addWire(NEW_ID); - module->addNotGate(NEW_ID, sig_d, new_sig_d); - module->addNotGate(NEW_ID, new_sig_q, sig_q); + module->addNotGate(NEW_ID, bit_d, new_bit_d); + module->addNotGate(NEW_ID, new_bit_q, bit_q); - cell->setPort("\\D", new_sig_d); - cell->setPort("\\Q", new_sig_q); + cell->setPort("\\D", new_bit_d); + cell->setPort("\\Q", new_bit_q); } for (auto wire : init_wires) diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index 9a6d69df0..9afbc0fce 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -81,7 +81,12 @@ struct Ice40FfssrPass : public Pass { for (auto cell : ff_cells) { - SigBit bit_d = sigmap(cell->getPort("\\D")); + SigSpec sig_d = cell->getPort("\\D"); + + if (GetSize(sig_d) < 1) + continue; + + SigBit bit_d = sigmap(sig_d[0]); if (sr_muxes.count(bit_d) == 0) continue; -- cgit v1.2.3