From 50ed34a6d0fe1013fae0a14165fc4fce1d1a3685 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 May 2019 11:26:18 -0700 Subject: opt_rmdff to work on $dffe and $_DFFE_* --- passes/opt/opt_rmdff.cc | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index e8570f0eb..a4ed582cb 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -260,8 +260,8 @@ delete_dlatch: bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) { - RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r; - RTLIL::Const val_cp, val_rp, val_rv; + RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r, sig_e; + RTLIL::Const val_cp, val_rp, val_rv, val_ep; if (dff->type == "$_FF_") { sig_d = dff->getPort("\\D"); @@ -285,6 +285,16 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); } + else if (dff->type.substr(0,7) == "$_DFFE_" && dff->type.substr(9) == "_" && + (dff->type[7] == 'N' || dff->type[7] == 'P') && + (dff->type[8] == 'N' || dff->type[8] == 'P')) { + sig_d = dff->getPort("\\D"); + sig_q = dff->getPort("\\Q"); + sig_c = dff->getPort("\\C"); + sig_e = dff->getPort("\\E"); + val_cp = RTLIL::Const(dff->type[6] == 'P', 1); + val_ep = RTLIL::Const(dff->type[7] == 'P', 1); + } else if (dff->type == "$ff") { sig_d = dff->getPort("\\D"); sig_q = dff->getPort("\\Q"); @@ -295,6 +305,14 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) sig_c = dff->getPort("\\CLK"); val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); } + else if (dff->type == "$dffe") { + sig_e = dff->getPort("\\EN"); + sig_d = dff->getPort("\\D"); + sig_q = dff->getPort("\\Q"); + sig_c = dff->getPort("\\CLK"); + val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); + val_ep = RTLIL::Const(dff->parameters["\\EN_POLARITY"].as_bool(), 1); + } else if (dff->type == "$adff") { sig_d = dff->getPort("\\D"); sig_q = dff->getPort("\\Q"); @@ -320,6 +338,16 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx); } + if (sig_e.size()) { + if (!sig_e.is_fully_const()) + return false; + if (sig_e != val_ep) { + if (has_init) + mod->connect(sig_q, val_init); + goto delete_dff; + } + } + if (dff->type.in("$ff", "$dff") && mux_drivers.has(sig_d)) { std::set muxes; mux_drivers.find(sig_d, muxes); @@ -489,7 +517,8 @@ struct OptRmdffPass : public Pass { if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_", "$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_", - "$ff", "$dff", "$adff")) + "$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_", + "$ff", "$dff", "$dffe", "$adff")) dff_list.push_back(cell->name); if (cell->type.in("$dlatch", "$_DLATCH_P_", "$_DLATCH_N_")) -- cgit v1.2.3 From 47f9ea142fcca94577519ede3de44b7c8b4f4379 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 May 2019 11:26:38 -0700 Subject: Add opt_rmdff tests --- tests/various/opt_rmdff.v | 30 ++++++++++++++++++++++++++++++ tests/various/opt_rmdff.ys | 25 +++++++++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 tests/various/opt_rmdff.v create mode 100644 tests/various/opt_rmdff.ys diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v new file mode 100644 index 000000000..224b8d418 --- /dev/null +++ b/tests/various/opt_rmdff.v @@ -0,0 +1,30 @@ +module opt_rmdff_test (input C, input D, input E, output reg [16:0] Q); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); +initial Q[1] = 1'b1; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep2 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[2])); +initial Q[3] = 1'b0; +\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[5])); +initial Q[6] = 1'b0; +\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep6 (.CLK(C), .D(D), .EN(E), .Q(Q[6])); + +\$_DFFE_PP_ remove7 (.C(C), .D(D), .E(1'b0), .Q(Q[7])); +initial Q[8] = 1'b1; +\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); +\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'bx), .Q(Q[9])); +\$_DFFE_PP_ keep10 (.C(C), .D(D), .E(1'b1), .Q(Q[10])); +initial Q[11] = 1'b0; +\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); + +\$_DFFE_NN_ remove12 (.C(C), .D(D), .E(1'b1), .Q(Q[12])); +initial Q[13] = 1'b1; +\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); +\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'bx), .Q(Q[14])); +\$_DFFE_NN_ keep15 (.C(C), .D(D), .E(1'b0), .Q(Q[15])); +initial Q[16] = 1'b0; +\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); + +endmodule diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys new file mode 100644 index 000000000..fffffb4b5 --- /dev/null +++ b/tests/various/opt_rmdff.ys @@ -0,0 +1,25 @@ +read_verilog -icells opt_rmdff.v +prep +design -stash gold +read_verilog -icells opt_rmdff.v +opt_rmdff + +select -assert-count 0 c:remove* +select -assert-min 7 c:keep* + +prep +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +equiv_make gold gate equiv +hierarchy -top equiv +equiv_simple -undef +equiv_status -assert + +design -load gold +stat + +design -load gate +stat -- cgit v1.2.3 From 5ac7e38d0aab1c73150accd9befbccc5398b8e42 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 May 2019 12:58:30 -0700 Subject: Fix spacing --- passes/opt/opt_rmdff.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index a4ed582cb..3cb8e2b1e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -342,8 +342,8 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) if (!sig_e.is_fully_const()) return false; if (sig_e != val_ep) { - if (has_init) - mod->connect(sig_q, val_init); + if (has_init) + mod->connect(sig_q, val_init); goto delete_dff; } } -- cgit v1.2.3 From 357b1de6bc3dcddc9bc0870e20c68c21c869a323 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 16:15:22 -0700 Subject: Resolve @cliffordwolf review, set even if !has_init --- passes/opt/opt_rmdff.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 3cb8e2b1e..a36b279c2 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -342,8 +342,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) if (!sig_e.is_fully_const()) return false; if (sig_e != val_ep) { - if (has_init) - mod->connect(sig_q, val_init); + mod->connect(sig_q, val_init); goto delete_dff; } } -- cgit v1.2.3 From 0d66103cbb462e6be613cc1187fa7be4f5ee4701 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 16:33:10 -0700 Subject: Add comments --- passes/opt/opt_rmdff.cc | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index a36b279c2..abbf8b5d1 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -364,39 +364,60 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) } } + // If clock is driven by a constant and (i) no reset signal + // (ii) Q has no initial value + // (iii) initial value is same as reset value if (!sig_c.empty() && sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) { if (val_rv.bits.size() == 0) val_rv = val_init; + // Q is permanently reset value or initial value mod->connect(sig_q, val_rv); goto delete_dff; } + // If D is fully undefined and reset signal present and (i) Q has no initial value + // (ii) initial value is same as reset value if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) { + // Q is permanently reset value mod->connect(sig_q, val_rv); goto delete_dff; } + // If D is fully undefined and no reset signal and Q has an initial value if (sig_d.is_fully_undef() && !sig_r.size() && has_init) { + // Q is permanently initial value mod->connect(sig_q, val_init); goto delete_dff; } + // If D is fully constant and (i) no reset signal + // (ii) reset value is same as constant D + // and (a) has initial value + // (b) initial value same as constant D if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) { + // Q is permanently D mod->connect(sig_q, sig_d); goto delete_dff; } + // If D input is same as Q output and (i) no reset signal + // (ii) no initial signal + // (iii) initial value is same as reset value if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) { + // Q is permanently reset value or initial value if (sig_r.size()) mod->connect(sig_q, val_rv); - if (has_init) + else if (has_init) mod->connect(sig_q, val_init); goto delete_dff; } + // If reset signal is present, and is fully constant if (!sig_r.empty() && sig_r.is_fully_const()) { + // If reset value is permanently enable or if reset is undefined if (sig_r == val_rp || sig_r.is_fully_undef()) { + // Q is permanently reset value mod->connect(sig_q, val_rv); goto delete_dff; } -- cgit v1.2.3 From f0c6b73b72b4ddc2b60865bcbd8934eba1bb6f52 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 17:44:57 -0700 Subject: Fix duplicate driver --- tests/various/opt_rmdff.v | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v index 224b8d418..7a165c231 100644 --- a/tests/various/opt_rmdff.v +++ b/tests/various/opt_rmdff.v @@ -3,28 +3,28 @@ module opt_rmdff_test (input C, input D, input E, output reg [16:0] Q); initial Q[1] = 1'b1; \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep2 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[2])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); initial Q[3] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4])); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[5])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); initial Q[6] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep6 (.CLK(C), .D(D), .EN(E), .Q(Q[6])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7])); -\$_DFFE_PP_ remove7 (.C(C), .D(D), .E(1'b0), .Q(Q[7])); -initial Q[8] = 1'b1; \$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); -\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'bx), .Q(Q[9])); -\$_DFFE_PP_ keep10 (.C(C), .D(D), .E(1'b1), .Q(Q[10])); -initial Q[11] = 1'b0; +initial Q[8] = 1'b1; +\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9])); +\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); \$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); +initial Q[12] = 1'b0; +\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12])); -\$_DFFE_NN_ remove12 (.C(C), .D(D), .E(1'b1), .Q(Q[12])); -initial Q[13] = 1'b1; \$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); -\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'bx), .Q(Q[14])); -\$_DFFE_NN_ keep15 (.C(C), .D(D), .E(1'b0), .Q(Q[15])); -initial Q[16] = 1'b0; +initial Q[14] = 1'b1; +\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14])); +\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); \$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); +initial Q[17] = 1'b0; +\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17])); endmodule -- cgit v1.2.3 From 822d0b7789fdfe94bfe11b96546af8430e5f3299 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 18:30:51 -0700 Subject: opt_rmdff to optimise even in presence of enable signal, even removing --- passes/opt/opt_rmdff.cc | 41 +++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index abbf8b5d1..d10cf508f 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -338,15 +338,6 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx); } - if (sig_e.size()) { - if (!sig_e.is_fully_const()) - return false; - if (sig_e != val_ep) { - mod->connect(sig_q, val_init); - goto delete_dff; - } - } - if (dff->type.in("$ff", "$dff") && mux_drivers.has(sig_d)) { std::set muxes; mux_drivers.find(sig_d, muxes); @@ -392,9 +383,11 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) // If D is fully constant and (i) no reset signal // (ii) reset value is same as constant D - // and (a) has initial value + // and (a) has no initial value // (b) initial value same as constant D - if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) { + // and (1) has no enable signal + // (2) enable is always active + if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const()) && (!sig_e.size() || (sig_d.is_fully_undef() && !has_init))) { // Q is permanently D mod->connect(sig_q, sig_d); goto delete_dff; @@ -415,7 +408,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) // If reset signal is present, and is fully constant if (!sig_r.empty() && sig_r.is_fully_const()) { - // If reset value is permanently enable or if reset is undefined + // If reset value is permanently active or if reset is undefined if (sig_r == val_rp || sig_r.is_fully_undef()) { // Q is permanently reset value mod->connect(sig_q, val_rv); @@ -437,6 +430,30 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) dff->unsetPort("\\R"); } + // If enable signal is present, and is fully constant + if (!sig_e.empty() && sig_e.is_fully_const()) + { + // If enable value is permanently inactive + if (sig_e != val_ep) { + // Q is permanently initial value + mod->connect(sig_q, val_init); + goto delete_dff; + } + + log("Removing unused enable from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); + + if (dff->type == "$dffe") { + dff->type = "$dff"; + dff->unsetPort("\\EN"); + dff->unsetParam("\\EN_POLARITY"); + return true; + } + + log_assert(dff->type.substr(0,7) == "$_DFFE_"); + dff->type = stringf("$_DFF_%c_", + dff->type[7]); + dff->unsetPort("\\E"); + } + return false; delete_dff: -- cgit v1.2.3 From 4bd9465ed3eb3ba2c0f45830b3337eaace4ec562 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 18:32:02 -0700 Subject: Call proc --- tests/various/opt_rmdff.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys index fffffb4b5..89cd3f0c8 100644 --- a/tests/various/opt_rmdff.ys +++ b/tests/various/opt_rmdff.ys @@ -2,12 +2,12 @@ read_verilog -icells opt_rmdff.v prep design -stash gold read_verilog -icells opt_rmdff.v +proc opt_rmdff select -assert-count 0 c:remove* select -assert-min 7 c:keep* -prep design -stash gate design -import gold -as gold -- cgit v1.2.3 From d15da4bc11c48d2eccb7fdc3543bf8176a281e1b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 18:33:18 -0700 Subject: Add more tests --- tests/various/opt_rmdff.v | 60 ++++++++++++++++++++++++++++++---------------- tests/various/opt_rmdff.ys | 1 + 2 files changed, 41 insertions(+), 20 deletions(-) diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v index 7a165c231..5d7d602c4 100644 --- a/tests/various/opt_rmdff.v +++ b/tests/various/opt_rmdff.v @@ -1,30 +1,50 @@ -module opt_rmdff_test (input C, input D, input E, output reg [16:0] Q); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); +module opt_rmdff_test (input C, input D, input E, output reg [29:0] Q); +//\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active initial Q[1] = 1'b1; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); // EN is never active +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active initial Q[3] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4])); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4])); // EN is always active +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care initial Q[6] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7])); +\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7])); // EN is non constant -\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); -initial Q[8] = 1'b1; -\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9])); -\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); -\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); +\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active +initial Q[9] = 1'b1; +\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9])); // EN is never active +\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care +\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active initial Q[12] = 1'b0; -\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12])); +\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12])); // EN is always active -\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); +\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active initial Q[14] = 1'b1; -\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14])); -\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); -\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); +\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14])); // EN is never active +\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care +\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active initial Q[17] = 1'b0; -\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17])); +\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17])); // EN is always active + +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(EN), .Q(Q[18])); // CLK is constant +initial Q[19] = 1'b1; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(EN), .Q(Q[19])); // CLK is constant +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(EN), .Q(Q[20])); // D is undriven, Q has no initial value +initial Q[21] = 1'b0; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(EN), .Q(Q[21])); // D is undriven, Q has initial value +//\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active +// // (TODO, Q starts with 1'bx and becomes 1'b0) +initial Q[23] = 1'b0; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[23])); // D is constant, initial Q value same as D, EN is always active +initial Q[24] = 1'b1; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q[24])); // D is constant, initial Q value NOT same as D, EN is always active +initial Q[25] = 1'b1; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[25])); // D is constant, EN is never active +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(EN), .Q(Q[28])); // EN is nonconst, but no initial value +initial Q[29] = 1'b1; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q[29])); // EN is always active, but with initial value endmodule diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys index 89cd3f0c8..081f81782 100644 --- a/tests/various/opt_rmdff.ys +++ b/tests/various/opt_rmdff.ys @@ -7,6 +7,7 @@ opt_rmdff select -assert-count 0 c:remove* select -assert-min 7 c:keep* +select -assert-count 0 t:$dffe 7:$_DFFE_* %u c:noenable* %i design -stash gate -- cgit v1.2.3 From e1cb1bb94815a60f81e8d5026b92864e7e4afe11 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 18:34:27 -0700 Subject: Fix typos --- tests/various/opt_rmdff.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v index 5d7d602c4..207eccc8e 100644 --- a/tests/various/opt_rmdff.v +++ b/tests/various/opt_rmdff.v @@ -1,5 +1,5 @@ module opt_rmdff_test (input C, input D, input E, output reg [29:0] Q); -//\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active initial Q[1] = 1'b1; \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); // EN is never active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care @@ -27,12 +27,12 @@ initial Q[14] = 1'b1; initial Q[17] = 1'b0; \$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17])); // EN is always active -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(EN), .Q(Q[18])); // CLK is constant +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant initial Q[19] = 1'b1; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(EN), .Q(Q[19])); // CLK is constant -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(EN), .Q(Q[20])); // D is undriven, Q has no initial value +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q[19])); // CLK is constant +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value initial Q[21] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(EN), .Q(Q[21])); // D is undriven, Q has initial value +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[21])); // D is undriven, Q has initial value //\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active // // (TODO, Q starts with 1'bx and becomes 1'b0) initial Q[23] = 1'b0; @@ -43,7 +43,7 @@ initial Q[25] = 1'b1; \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[25])); // D is constant, EN is never active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(EN), .Q(Q[28])); // EN is nonconst, but no initial value +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value initial Q[29] = 1'b1; \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q[29])); // EN is always active, but with initial value -- cgit v1.2.3 From f3e86e06e698491b110ac66b88bc3c0ce3cda174 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 18:43:26 -0700 Subject: Fix init --- tests/various/opt_rmdff.v | 54 +++++++++++++++++++++++------------------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v index 207eccc8e..b1c06703c 100644 --- a/tests/various/opt_rmdff.v +++ b/tests/various/opt_rmdff.v @@ -1,50 +1,50 @@ -module opt_rmdff_test (input C, input D, input E, output reg [29:0] Q); +module opt_rmdff_test (input C, input D, input E, output [29:0] Q); \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active -initial Q[1] = 1'b1; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[1])); // EN is never active +(* init = "1'b1" *) wire Q1; assign Q[1] = Q1; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q1)); // EN is never active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active -initial Q[3] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[4])); // EN is always active +(* init = "1'b0" *) wire Q4; assign Q[4] = Q4; +\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q4)); // EN is always active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care -initial Q[6] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q[7])); // EN is non constant +(* init = "1'b0" *) wire Q7; assign Q[7] = Q7; +\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q7)); // EN is non constant \$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active -initial Q[9] = 1'b1; -\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q[9])); // EN is never active +(* init = "1'b1" *) wire Q9; assign Q[9] = Q9; +\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q9)); // EN is never active \$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care \$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active -initial Q[12] = 1'b0; -\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q[12])); // EN is always active +(* init = "1'b0" *) wire Q12; assign Q[12] = Q12; +\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q12)); // EN is always active \$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active -initial Q[14] = 1'b1; -\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q[14])); // EN is never active +(* init = "1'b1" *) wire Q14; assign Q[14] = Q14; +\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q14)); // EN is never active \$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care \$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active -initial Q[17] = 1'b0; -\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q[17])); // EN is always active +(* init = "1'b0" *) wire Q17; assign Q[17] = Q17; +\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q17)); // EN is always active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant -initial Q[19] = 1'b1; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q[19])); // CLK is constant +(* init = "1'b1" *) wire Q19; assign Q[19] = Q19; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q19)); // CLK is constant \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value -initial Q[21] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[21])); // D is undriven, Q has initial value +(* init = "1'b0" *) wire Q21; assign Q[21] = Q21; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q21)); // D is undriven, Q has initial value //\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active // // (TODO, Q starts with 1'bx and becomes 1'b0) -initial Q[23] = 1'b0; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[23])); // D is constant, initial Q value same as D, EN is always active -initial Q[24] = 1'b1; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q[24])); // D is constant, initial Q value NOT same as D, EN is always active -initial Q[25] = 1'b1; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[25])); // D is constant, EN is never active +(* init = "1'b0" *) wire Q23; assign Q[23] = Q23; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q23)); // D is constant, initial Q value same as D, EN is always active +(* init = "1'b1" *) wire Q24; assign Q[24] = Q24; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q24)); // D is constant, initial Q value NOT same as D, EN is always active +(* init = "1'b1" *) wire Q25; assign Q[25] = Q25; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q25)); // D is constant, EN is never active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value \$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value -initial Q[29] = 1'b1; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q[29])); // EN is always active, but with initial value +(* init = "1'b1" *) wire Q29; assign Q[29] = Q29; +\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q29)); // EN is always active, but with initial value endmodule -- cgit v1.2.3 From d4fb6cac7c4c93f868e294dfc95936516813eeac Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 25 May 2019 12:55:57 -0700 Subject: Revert enable check --- passes/opt/opt_rmdff.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index d10cf508f..2abffa2a9 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -385,9 +385,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) // (ii) reset value is same as constant D // and (a) has no initial value // (b) initial value same as constant D - // and (1) has no enable signal - // (2) enable is always active - if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const()) && (!sig_e.size() || (sig_d.is_fully_undef() && !has_init))) { + if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) { // Q is permanently D mod->connect(sig_q, sig_d); goto delete_dff; -- cgit v1.2.3